公开(公告)号：US20110018050A1

公开(公告)日：2011-01-27

申请号：US12727830

申请日：2010-03-19

申请人： Tomoko FUJIWARA ,  Ryota Katsumata ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Megumi Ishiduki ,  Junya Matsunami ,  Hideaki Aochi ,  Ryouhei Kirisawa ,  Yoshimasa Mikajiri ,  Shigeto Oota

发明人： Tomoko FUJIWARA ,  Ryota Katsumata ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Megumi Ishiduki ,  Junya Matsunami ,  Hideaki Aochi ,  Ryouhei Kirisawa ,  Yoshimasa Mikajiri ,  Shigeto Oota

IPC分类号： H01L29/51 ,  H01L21/4763

CPC分类号： H01L27/11551 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11556

摘要： A nonvolatile semiconductor memory device, includes: a stacked structural unit including electrode films alternately stacked with inter-electrode insulating films; first and second semiconductor pillars piercing the stacked structural unit; a connection portion semiconductor layer electrically connect the first and second semiconductor pillars; a connection portion conductive layer provided to oppose the connection portion semiconductor layer; a memory layer and an inner insulating film provided between the first and semiconductor pillars and each of the electrode films, and between the connection portion conductive layer and the connection portion semiconductor layer; an outer insulating film provided between the memory layer and each of the electrode films; and a connection portion outer insulating film provided between the memory layer and the connection portion conductive layer. The connection portion outer insulating film has a film thickness thicker than a film thickness of the outer insulating film.

摘要翻译： 一种非易失性半导体存储器件，包括：堆叠结构单元，其包括交替层叠有电极间绝缘膜的电极膜; 第一和第二半导体柱刺穿堆叠结构单元; 连接部分半导体层电连接第一和第二半导体柱; 连接部分导电层，设置成与连接部分半导体层相对; 设置在所述第一半导体柱和所述半导体柱之间以及所述电极膜之间并且位于所述连接部分导电层和所述连接部半导体层之间的存储层和内部绝缘膜; 设置在所述存储层和每个所述电极膜之间的外部绝缘膜; 以及设置在存储层和连接部分导电层之间的连接部分外绝缘膜。 连接部外绝缘膜的膜厚比外绝缘膜的膜厚厚。

公开(公告)号：US08541866B2

公开(公告)日：2013-09-24

申请号：US12722920

申请日：2010-03-12

申请人： Ryota Katsumata ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Megumi Ishiduki ,  Hideaki Aochi ,  Ryouhei Kirisawa ,  Junya Matsunami ,  Tomoko Fujiwara

发明人： Ryota Katsumata ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Megumi Ishiduki ,  Hideaki Aochi ,  Ryouhei Kirisawa ,  Junya Matsunami ,  Tomoko Fujiwara

IPC分类号： H01L29/00

CPC分类号： H01L27/1021 ,  H01L23/5252 ,  H01L27/0207 ,  H01L27/101 ,  H01L27/112 ,  H01L27/11206 ,  H01L2924/0002 ,  H01L2924/00

摘要： A nonvolatile semiconductor memory device, includes: a stacked structural unit including a plurality of stacked component units stacked in a first direction, each of the stacked component units including a first conducting film made of a semiconductor of a first conductivity type provided perpendicular to the first direction and a first insulating film stacked in the first direction with the first conducting film; a semiconductor pillar piercing the stacked structural unit in the first direction and including a conducting region of a second conductivity type, the semiconductor pillar including a first region opposing each of the first conducting films, and a second region provided between the first regions with respect to the first direction, the second region having a resistance different from a resistance of the first region; and a second insulating film provided between the semiconductor pillar and the first conducting film.

摘要翻译： 一种非易失性半导体存储器件，包括：堆叠结构单元，包括沿第一方向堆叠的多个堆叠的元件单元，每个堆叠元件单元包括由垂直于第一元件垂直设置的第一导电类型的半导体制成的第一导电膜 方向和与第一导电膜在第一方向上堆叠的第一绝缘膜; 所述半导体柱在所述第一方向上穿透所述层叠结构单元，并且包括第二导电类型的导电区域，所述半导体柱包括与所述第一导电膜相对的第一区域，以及设置在所述第一区域之间的第二区域， 所述第一方向，所述第二区域具有与所述第一区域的电阻不同的电阻; 以及设置在所述半导体柱和所述第一导电膜之间的第二绝缘膜。

公开(公告)号：US20130077461A1

公开(公告)日：2013-03-28

申请号：US13423755

申请日：2012-03-19

申请人： Akihiro Koga ,  Yasushi Tomizawa ,  Hideo Shinomiya ,  Moto Yabuki ,  Jun Hirota ,  Yoshihisa Iwata ,  Masayuki Ichige ,  Kikuko Sugimae ,  Junya Matsunami

发明人： Akihiro Koga ,  Yasushi Tomizawa ,  Hideo Shinomiya ,  Moto Yabuki ,  Jun Hirota ,  Yoshihisa Iwata ,  Masayuki Ichige ,  Kikuko Sugimae ,  Junya Matsunami

IPC分类号： G11B9/00

CPC分类号： G11B9/02 ,  G11B9/1418 ,  G11B9/1436

摘要： A storage device includes a recording medium, a probe, a substrate, and a processing unit. The recording medium stores a signal. The probe reads or writes the signal to/from the recording medium. The substrate is provided with the probe via a conductive anchor interposed therebetween and a first connection terminal connected to the probe. The processing unit is provided on the substrate and has a second connection terminal. The second connection terminal is connected to the first connection terminal.

摘要翻译： 存储装置包括记录介质，探针，基板和处理单元。 记录介质存储信号。 探头将信号读取或写入记录介质。 基板经由插入其间的导电锚固体和连接到探针的第一连接端子设置有探针。 处理单元设置在基板上，并具有第二连接端子。 第二连接端子连接到第一连接端子。

公开(公告)号：US08374033B2

公开(公告)日：2013-02-12

申请号：US12728694

申请日：2010-03-22

申请人： Masaru Kito ,  Ryota Katsumata ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Megumi Ishiduki ,  Junya Matsunami ,  Tomoko Fujiwara ,  Hideaki Aochi ,  Ryouhei Kirisawa ,  Yoshimasa Mikajiri ,  Shigeto Oota

发明人： Masaru Kito ,  Ryota Katsumata ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Megumi Ishiduki ,  Junya Matsunami ,  Tomoko Fujiwara ,  Hideaki Aochi ,  Ryouhei Kirisawa ,  Yoshimasa Mikajiri ,  Shigeto Oota

IPC分类号： G11C16/04

CPC分类号： G11C16/04 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/16 ,  G11C16/3409 ,  G11C16/3413 ,  H01L27/11578 ,  H01L27/11582

摘要： A nonvolatile semiconductor memory device includes: a memory unit; and a control unit. The memory unit includes a multilayer structure including electrode films and inter-electrode insulating films alternately stacked in a first direction; a semiconductor pillar piercing the multilayer structure in the first direction; a memory layer provided between the semiconductor pillar and the electrode films; a inner insulating film provided between the memory layer and the semiconductor pillar; a outer insulating film provided between the memory layer and the electrode films; and a wiring electrically connected to the first semiconductor pillar. In erasing operation, the control unit sets the first wiring at a first potential and sets the electrode film at a second potential lower than the first potential, and then sets the first wiring at a third potential and sets the electrode film at a fourth potential higher than the third potential.

摘要翻译： 非易失性半导体存储器件包括：存储器单元; 和控制单元。 存储单元包括多层结构，其包括沿第一方向交替堆叠的电极膜和电极间绝缘膜; 在所述第一方向上穿透所述多层结构的半导体柱; 设置在所述半导体柱和所述电极膜之间的存储层; 设置在所述存储层和所述半导体柱之间的内部绝缘膜; 设置在存储层和电极膜之间的外部绝缘膜; 以及电连接到第一半导体柱的布线。 在擦除操作中，控制单元将第一布线设置在第一电位，并将电极膜设置在比第一电位低的第二电位，然后将第一布线设置在第三电位，并将电极膜设置为高于第四电位 比第三个潜力。

公开(公告)号：US08264031B2

公开(公告)日：2012-09-11

申请号：US12696544

申请日：2010-01-29

申请人： Masaru Kidoh ,  Hiroyasu Tanaka ,  Tomoko Fujiwara ,  Megumi Ishiduki ,  Yosuke Komori ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Ryota Katsumata ,  Ryouhei Kirisawa ,  Junya Matsunami ,  Hideaki Aochi

发明人： Masaru Kidoh ,  Hiroyasu Tanaka ,  Tomoko Fujiwara ,  Megumi Ishiduki ,  Yosuke Komori ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Ryota Katsumata ,  Ryouhei Kirisawa ,  Junya Matsunami ,  Hideaki Aochi

IPC分类号： H01L29/792

CPC分类号： H01L27/11578 ,  H01L27/11551 ,  H01L27/11556

摘要： A nonvolatile semiconductor memory device includes: a semiconductor substrate; a multilayer structure; a semiconductor pillar; a third insulating film; and a fourth insulating film layer. The a multilayer structure is provided on the semiconductor substrate and including a plurality of constituent multilayer bodies stacked in a first direction perpendicular to a major surface of the semiconductor substrate. Each of the plurality of constituent multilayer bodies includes an electrode film provided parallel to the major surface, a first insulating film, a charge storage layer provided between the electrode film and the first insulating film, and a second insulating film provided between the charge storage layer and the electrode film. The semiconductor pillar penetrates through the multilayer structure in the first direction. The third insulating film is provided between the semiconductor pillar and the electrode film. The fourth insulating film is provided between the semiconductor pillar and the charge storage layer.

摘要翻译： 非易失性半导体存储器件包括：半导体衬底; 多层结构; 半导体柱; 第三绝缘膜; 和第四绝缘膜层。 多层结构设置在半导体衬底上，并且包括沿垂直于半导体衬底的主表面的第一方向堆叠的多个构成层叠体。 多个构成多层体中的每一个包括平行于主表面设置的电极膜，第一绝缘膜，设置在电极膜和第一绝缘膜之间的电荷存储层，以及设置在电荷存储层 和电极膜。 半导体柱沿第一方向穿透多层结构。 第三绝缘膜设置在半导体柱和电极膜之间。 第四绝缘膜设置在半导体柱和电荷存储层之间。

公开(公告)号：US20110103153A1

公开(公告)日：2011-05-05

申请号：US12851054

申请日：2010-08-05

申请人： Ryota KATSUMATA ,  Hideaki Aochi ,  Hiroyasu Tanaka ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Yosuke Komori ,  Megumi Ishiduki ,  Junya Matsunami ,  Tomoko Fujiwara ,  Ryouhei Kirisawa ,  Yoshimasa Mikajiri ,  Shigeto Oota

发明人： Ryota KATSUMATA ,  Hideaki Aochi ,  Hiroyasu Tanaka ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Yosuke Komori ,  Megumi Ishiduki ,  Junya Matsunami ,  Tomoko Fujiwara ,  Ryouhei Kirisawa ,  Yoshimasa Mikajiri ,  Shigeto Oota

IPC分类号： G11C16/06 ,  H01L29/792

CPC分类号： H01L27/11578 ,  G11C16/0466 ,  G11C16/06 ,  H01L27/11565 ,  H01L27/11582

摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a substrate, a stacked body, a semiconductor pillar, a charge storage film, and a drive circuit. The stacked body is provided on the substrate. The stacked body includes a plurality of insulating films alternately stacked with a plurality of electrode films. A through-hole is made in the stacked body to align in a stacking direction. The semiconductor pillar is buried in an interior of the through-hole. The charge storage film is provided between the electrode film and the semiconductor pillar. The drive circuit supplies a potential to the electrode film. The diameter of the through-hole differs by a position in the stacking direction. The drive circuit supplies a potential to reduce a potential difference with the semiconductor pillar as a diameter of the through-hole piercing the electrode film decreases.

摘要翻译： 根据一个实施例，非易失性半导体存储器件包括衬底，堆叠体，半导体柱，电荷存储膜和驱动电路。 层叠体设置在基板上。 层叠体包括交替层叠有多个电极膜的多个绝缘膜。 在堆叠体中形成通孔，以在堆叠方向上对齐。 半导体柱被埋在通孔的内部。 电荷存储膜设置在电极膜和半导体柱之间。 驱动电路为电极膜提供电位。 通孔的直径与层叠方向的位置不同。 当穿透电极膜的通孔的直径减小时，驱动电路提供降低与半导体柱的电位差的电位。

公开(公告)号：US20110002172A1

公开(公告)日：2011-01-06

申请号：US12728694

申请日：2010-03-22

申请人： Masaru KITO ,  Ryota Katsumata ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Megumi Ishiduki ,  Junya Matsunami ,  Tomoko Fujiwara ,  Hideaki Aochi ,  Ryouhei Kirisawa ,  Yoshimasa Mikajiri ,  Shigeto Oota

发明人： Masaru KITO ,  Ryota Katsumata ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Megumi Ishiduki ,  Junya Matsunami ,  Tomoko Fujiwara ,  Hideaki Aochi ,  Ryouhei Kirisawa ,  Yoshimasa Mikajiri ,  Shigeto Oota

IPC分类号： G11C16/02 ,  G11C11/34

CPC分类号： G11C16/04 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/16 ,  G11C16/3409 ,  G11C16/3413 ,  H01L27/11578 ,  H01L27/11582

摘要： A nonvolatile semiconductor memory device includes: a memory unit; and a control unit. The memory unit includes a multilayer structure including electrode films and inter-electrode insulating films alternately stacked in a first direction; a semiconductor pillar piercing the multilayer structure in the first direction; a memory layer provided between the semiconductor pillar and the electrode films; a inner insulating film provided between the memory layer and the semiconductor pillar; a outer insulating film provided between the memory layer and the electrode films; and a wiring electrically connected to the first semiconductor pillar. In erasing operation, the control unit sets the first wiring at a first potential and sets the electrode film at a second potential lower than the first potential, and then sets the first wiring at a third potential and sets the electrode film at a fourth potential higher than the third potential.

摘要翻译： 非易失性半导体存储器件包括：存储器单元; 和控制单元。 存储单元包括多层结构，其包括沿第一方向交替堆叠的电极膜和电极间绝缘膜; 在所述第一方向上穿透所述多层结构的半导体柱; 设置在所述半导体柱和所述电极膜之间的存储层; 设置在所述存储层和所述半导体柱之间的内部绝缘膜; 设置在存储层和电极膜之间的外部绝缘膜; 以及电连接到第一半导体柱的布线。 在擦除操作中，控制单元将第一布线设置在第一电位，并将电极膜设置在比第一电位低的第二电位，然后将第一布线设置在第三电位，并将电极膜设置为高于第四电位 比第三个潜力。

公开(公告)号：US20100327339A1

公开(公告)日：2010-12-30

申请号：US12728727

申请日：2010-03-22

申请人： Hiroyasu TANAKA ,  Ryota Katsumata ,  Hideaki Aochi ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Yosuke Komori ,  Megumi Ishiduki ,  Junya Matsunami ,  Tomoko Fujiwara ,  Ryouhei Kirisawa ,  Yoshimasa Mikajiri ,  Shigeto Oota

发明人： Hiroyasu TANAKA ,  Ryota Katsumata ,  Hideaki Aochi ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Yosuke Komori ,  Megumi Ishiduki ,  Junya Matsunami ,  Tomoko Fujiwara ,  Ryouhei Kirisawa ,  Yoshimasa Mikajiri ,  Shigeto Oota

IPC分类号： H01L27/115 ,  H01L21/8246

CPC分类号： H01L27/11578 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

摘要： A semiconductor memory device provided with a cell array section and a peripheral circuit section, the device includes: a back gate electrode; a stacked body provided on the back gate electrode; a plurality of semiconductor pillars extending in a stacking direction; connection members, each of the connection members connecting one of the semiconductor pillars to another one of the semiconductor pillars; a back-gate electrode contact applying a potential to the back gate electrode; a gate electrode provided in the peripheral circuit section; and a gate electrode contact applying a potential to the gate electrode, the back gate electrode and the gate electrode respectively including: a lower semiconductor layer; a conductive layer provided on the lower semiconductor layer; and an upper semiconductor layer provided on the conductive layer, the connection members being provided in or on the upper semiconductor layer, the back-gate electrode contact and the gate electrode contact being in contact with the conductive layer.

摘要翻译： 一种设置有单元阵列部分和外围电路部分的半导体存储器件，该器件包括：背栅电极; 设置在所述背栅电极上的层叠体; 沿层叠方向延伸的多个半导体柱; 连接构件，每个连接构件将半导体柱之一连接到另一个半导体柱; 向所述背栅电极施加电位的背栅极电极接触; 设置在所述外围电路部中的栅电极; 以及向所述栅电极，所述背栅电极和所述栅电极施加电位的栅电极接触部，分别包括：下半导体层; 设置在下半导体层上的导电层; 以及设置在所述导电层上的上半导体层，所述连接构件设置在所述上​​半导体层中或所述上半导体层上，所述背栅电极接触和所述栅电极接触与所述导电层接触。

公开(公告)号：US20100244186A1

公开(公告)日：2010-09-30

申请号：US12722920

申请日：2010-03-12

申请人： Ryota KATSUMATA ,  Masaru KITO ,  Yoshiaki FUKUZUMI ,  Masaru KIDOH ,  Hiroyasu TANAKA ,  Yosuke KOMORI ,  Megumi ISHIDUKI ,  Hideaki AOCHI ,  Ryouhei KIRISAWA ,  Junya MATSUNAMI ,  Tomoko FUJIWARA

发明人： Ryota KATSUMATA ,  Masaru KITO ,  Yoshiaki FUKUZUMI ,  Masaru KIDOH ,  Hiroyasu TANAKA ,  Yosuke KOMORI ,  Megumi ISHIDUKI ,  Hideaki AOCHI ,  Ryouhei KIRISAWA ,  Junya MATSUNAMI ,  Tomoko FUJIWARA

IPC分类号： H01L27/10 ,  H01L21/822 ,  G11C17/16

CPC分类号： H01L27/1021 ,  H01L23/5252 ,  H01L27/0207 ,  H01L27/101 ,  H01L27/112 ,  H01L27/11206 ,  H01L2924/0002 ,  H01L2924/00

摘要： A nonvolatile semiconductor memory device, includes: a stacked structural unit including a plurality of stacked component units stacked in a first direction, each of the stacked component units including a first conducting film made of a semiconductor of a first conductivity type provided perpendicular to the first direction and a first insulating film stacked in the first direction with the first conducting film; a semiconductor pillar piercing the stacked structural unit in the first direction and including a conducting region of a second conductivity type, the semiconductor pillar including a first region opposing each of the first conducting films, and a second region provided between the first regions with respect to the first direction, the second region having a resistance different from a resistance of the first region; and a second insulating film provided between the semiconductor pillar and the first conducting film.

摘要翻译： 一种非易失性半导体存储器件，包括：堆叠结构单元，包括沿第一方向堆叠的多个堆叠的元件单元，每个堆叠元件单元包括由垂直于第一元件垂直设置的第一导电类型的半导体制成的第一导电膜 方向和与第一导电膜在第一方向上堆叠的第一绝缘膜; 所述半导体柱在所述第一方向上穿透所述层叠结构单元，并且包括第二导电类型的导电区域，所述半导体柱包括与所述第一导电膜相对的第一区域，以及设置在所述第一区域之间的第二区域， 所述第一方向，所述第二区域具有与所述第一区域的电阻不同的电阻; 以及设置在所述半导体柱和所述第一导电膜之间的第二绝缘膜。

公开(公告)号：US20100244119A1

公开(公告)日：2010-09-30

申请号：US12724713

申请日：2010-03-16

申请人： Yoshiaki Fukuzumi ,  Ryota Katsumata ,  Masaru Kito ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Megumi Ishiduki ,  Junya Matsunami ,  Tomoko Fujiwara ,  Hideaki Aochi ,  Ryouhei Kirisawa ,  Yoshimasa Mikajiri ,  Shigeto Oota

发明人： Yoshiaki Fukuzumi ,  Ryota Katsumata ,  Masaru Kito ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Megumi Ishiduki ,  Junya Matsunami ,  Tomoko Fujiwara ,  Hideaki Aochi ,  Ryouhei Kirisawa ,  Yoshimasa Mikajiri ,  Shigeto Oota

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L27/11582 ,  H01L21/223 ,  H01L21/265 ,  H01L27/11578 ,  H01L29/04 ,  H01L29/1037 ,  H01L29/16 ,  H01L29/42344 ,  H01L29/4916 ,  H01L29/66666 ,  H01L29/66833 ,  H01L29/7827 ,  H01L29/792 ,  H01L29/7926

摘要： A nonvolatile semiconductor memory device, includes: a stacked structural unit including a plurality of insulating films alternately stacked with a plurality of electrode films in a first direction; a selection gate electrode stacked on the stacked structural unit in the first direction; an insulating layer stacked on the selection gate electrode in the first direction; a first semiconductor pillar piercing the stacked structural unit, the selection gate electrode, and the insulating layer in the first direction, a first cross section of the first semiconductor pillar having an annular configuration, the first cross section being cut in a plane orthogonal to the first direction; a first core unit buried in an inner side of the first semiconductor pillar, the first core unit being recessed from an upper face of the insulating layer; and a first conducting layer of the first semiconductor pillar provided on the first core unit to contact the first core unit.

摘要翻译： 一种非易失性半导体存储器件，包括：堆叠结构单元，包括在第一方向上交替地堆叠有多个电极膜的多个绝缘膜; 选择栅极电极，其沿所述第一方向堆叠在所述层叠结构单元上; 绝缘层，其沿所述第一方向堆叠在所述选择栅电极上; 第一半导体柱在第一方向上穿透层叠结构单元，选择栅电极和绝缘层，第一半导体柱的第一截面具有环形构造，第一横截面在垂直于 第一方向 第一核心单元，其被埋在第一半导体柱的内侧，第一芯单元从绝缘层的上表面凹入; 以及设置在所述第一芯单元上以接触所述第一芯单元的所述第一半导体柱的第一导电层。