公开(公告)号：US08692312B2

公开(公告)日：2014-04-08

申请号：US13428506

申请日：2012-03-23

申请人： Yoshiaki Fukuzumi ,  Masaru Kito ,  Takeshi Imamura

发明人： Yoshiaki Fukuzumi ,  Masaru Kito ,  Takeshi Imamura

IPC分类号： H01L29/792

CPC分类号： H01L29/7926 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/66833

摘要： According to one embodiment, a method of manufacturing a semiconductor memory device is provided. In the method, a laminated body in which a first silicon layer, a first sacrificial layer, a second silicon layer, and a second sacrificial layer are laminated in turn is formed. A first insulating film is formed on the laminated body. A trench is formed in the laminated body and the first insulating film. A third sacrificial layer is formed into the trench. The third sacrificial layer is etched by wet etching to be retreated from a top surface of the third sacrificial layer, thereby etching end faces of the first sacrificial layer and the second sacrificial layer.

摘要翻译： 根据一个实施例，提供一种制造半导体存储器件的方法。 在该方法中，形成依次层叠有第一硅层，第一牺牲层，第二硅层和第二牺牲层的层叠体。 第一绝缘膜形成在层叠体上。 在层叠体和第一绝缘膜中形成沟槽。 第三牺牲层形成在沟槽中。 通过湿蚀刻蚀刻第三牺牲层以从第三牺牲层的顶表面撤回，从而蚀刻第一牺牲层和第二牺牲层的端面。

公开(公告)号：US08653577B2

公开(公告)日：2014-02-18

申请号：US13003644

申请日：2009-07-01

申请人： Yoshiaki Fukuzumi ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Megumi Ishiduki ,  Masaru Kito ,  Hideaki Aochi ,  Ryota Katsumata ,  Masaru Kidoh

发明人： Yoshiaki Fukuzumi ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Megumi Ishiduki ,  Masaru Kito ,  Hideaki Aochi ,  Ryota Katsumata ,  Masaru Kidoh

IPC分类号： H01L29/788 ,  H01L29/792

CPC分类号： H01L29/7926 ,  G11C16/0466 ,  H01L27/11565 ,  H01L27/11578 ,  H01L27/11582

摘要： A nonvolatile semiconductor memory device includes: a stacked body in which insulating films and electrode films are alternately stacked; selection gate electrodes provided on the stacked body; bit lines provided on the selection gate electrodes; semiconductor pillars; connective members separated from one another; and a charge storage layer provided between the electrode film and the semiconductor pillar. One of the connective members is connected between a lower part of one of the semiconductor pillars and a lower part of another of the semiconductor pillars. The one of the semiconductor pillars passes through one of the selection gate electrodes and is connected to one of the bit lines, and the another of the semiconductor pillars passes through another of the selection gate electrodes and is connected to another of the bit lines.

摘要翻译： 非易失性半导体存储器件包括：绝缘膜和电极膜交替层叠的层叠体; 设置在层叠体上的选择栅电极; 设置在选择栅电极上的位线; 半导体柱 连接成员彼此分离; 以及设置在电极膜和半导体柱之间的电荷存储层。 一个连接构件连接在一个半导体柱的下部和另一个半导体柱的下部之间。 半导体柱中的一个穿过选择栅极之一并连接到一个位线，并且另一个半导体柱通过另一个选择栅电极并连接到另一个位线。

公开(公告)号：US08624316B2

公开(公告)日：2014-01-07

申请号：US13227882

申请日：2011-09-08

申请人： Ichiro Mizushima ,  Yoshiaki Fukuzumi ,  Shinji Mori

发明人： Ichiro Mizushima ,  Yoshiaki Fukuzumi ,  Shinji Mori

IPC分类号： H01L29/792

CPC分类号： H01L21/28282 ,  H01L27/11582 ,  H01L29/42352

摘要： According to one embodiment, a semiconductor device, including a substrate, a stacked layer body provided above the substrate, the stacked layer body alternately stacking an insulator and an electrode film one on another, silicon pillars contained with fluorine, the silicon pillar penetrating through and provided in the stacked layer body, a tunnel insulator provided on a surface of the silicon pillar facing to the stacked layer body, a charge storage layer provided on a surface of the tunnel insulator facing to the stacked layer body, a block insulator provided on a surface of the charge storage layer facing to the stacked layer body, the block insulator being in contact with the electrode film, and an embedded portion provided in the silicon pillars.

摘要翻译： 根据一个实施例，一种半导体器件，包括衬底，在衬底上方设置的层叠体，堆叠层体彼此交替堆叠绝缘体和电极膜，含有氟的硅柱，穿透硅柱的硅柱， 设置在堆叠层体上的隧道绝缘体，设置在与层叠体主体相对的硅柱的表面上的隧道绝缘体，设置在隧道绝缘体的面向堆叠层主体的表面上的电荷存储层， 面向堆叠层体的电荷存储层的表面，块绝缘体与电极膜接触，以及设置在硅柱中的嵌入部。

公开(公告)号：US08598643B2

公开(公告)日：2013-12-03

申请号：US13235425

申请日：2011-09-18

申请人： Kaori Kawasaki ,  Yoshiaki Fukuzumi ,  Masaru Kito ,  Tomoko Fujiwara ,  Takeshi Imamura ,  Ryouhei Kirisawa ,  Hideaki Aochi

发明人： Kaori Kawasaki ,  Yoshiaki Fukuzumi ,  Masaru Kito ,  Tomoko Fujiwara ,  Takeshi Imamura ,  Ryouhei Kirisawa ,  Hideaki Aochi

IPC分类号： H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L27/11582 ,  H01L27/1157 ,  H01L29/7926

摘要： According to one embodiment, a nonvolatile semiconductor memory device comprises a first conductive layer, a second conductive layer, a first inter-electrode insulating film, and a third conductive layer stacked above the first conductive layer, a memory film, a semiconductor layer, an insulating member, and a silicide layer. The memory film and the semiconductor layer is formed on the inner surface of through hole provided in the second conductive layer, the first inter-electrode insulating film, and the third conductive layer. The insulating member is buried in a slit dividing the second conductive layer, the first inter-electrode insulating film, and the third conductive layer. The silicide layer is formed on surfaces of the second conductive layer and the third conductive layer in the slit. The distance between the second conductive layer and the third conductive layer along the inner surface of the slit is longer than that of along the stacking direction.

摘要翻译： 根据一个实施例，非易失性半导体存储器件包括第一导电层，第二导电层，第一电极间绝缘膜和堆叠在第一导电层上方的第三导电层，存储膜，半导体层， 绝缘构件和硅化物层。 存储膜和半导体层形成在设置在第二导电层，第一电极间绝缘膜和第三导电层中的通孔的内表面上。 绝缘构件埋设在分割第二导电层，第一电极间绝缘膜和第三导电层的狭缝中。 硅化物层形成在狭缝中的第二导电层和第三导电层的表面上。 沿着狭缝的内表面，第二导电层和第三导电层之间的距离比层叠方向长。

公开(公告)号：US08581305B2

公开(公告)日：2013-11-12

申请号：US13046894

申请日：2011-03-14

申请人： Yoshiaki Fukuzumi ,  Hideaki Aochi

发明人： Yoshiaki Fukuzumi ,  Hideaki Aochi

IPC分类号： H01L23/525

CPC分类号： H01L27/2463 ,  G11C13/0007 ,  G11C16/04 ,  G11C2213/73 ,  H01L23/525 ,  H01L23/528 ,  H01L27/2436 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor memory device according to one embodiment of the present invention includes a dielectric film configured to store information depending on presence or absence of a conductive path therein, and a plurality of electrodes provided to contact a first surface of the dielectric film. The conductive path can be formed between two electrodes arbitrarily selected form the plurality of electrodes. The conductive path has a rectifying property of allowing a current to flow more easily in a first direction connecting arbitrary two electrodes than in a second direction opposite to the first direction. The largest possible number of the conductive paths that may be formed is larger than the number of the plurality of electrodes.

摘要翻译： 根据本发明的一个实施例的半导体存储器件包括：电介质膜，被配置为根据存在或不存在导电路径来存储信息;以及多个电极，设置成与电介质膜的第一表面接触。 导电路径可以形成在从多个电极任意选择的两个电极之间。 导电路径具有使电流在连接任意两个电极的第一方向上比在与第一方向相反的第二方向更容易流动的整流特性。 可能形成的最大可能数量的导电路径大于多个电极的数量。

公开(公告)号：US20130242670A1

公开(公告)日：2013-09-19

申请号：US13601539

申请日：2012-08-31

申请人： Shigeki Hattori ,  Masakazu Yamagiwa ,  Masaya Terai ,  Hideyuki Nishizawa ,  Koji Asakawa ,  Yoshiaki Fukuzumi

发明人： Shigeki Hattori ,  Masakazu Yamagiwa ,  Masaya Terai ,  Hideyuki Nishizawa ,  Koji Asakawa ,  Yoshiaki Fukuzumi

IPC分类号： H01L29/788 ,  G11C16/04

CPC分类号： H01L21/28273 ,  B82Y10/00 ,  G11C16/0416 ,  G11C16/0483 ,  H01L27/11556 ,  H01L29/42332 ,  H01L29/7881

摘要： A nonvolatile semiconductor storage device includes a semiconductor layer, a first insulating film formed on the semiconductor layer, a charge storage layer formed on the first insulating film and having fine metal grains, a second insulating film formed on the charge storage layer, and a gate electrode formed on the second insulating film. During a write operation, a differential voltage is applied across the gate electrode and the semiconductor layer to place the gate electrode at a lower voltage than the semiconductor layer and cause a positive electric charge to be stored in the charge storage layer.

摘要翻译： 非易失性半导体存储装置包括半导体层，形成在半导体层上的第一绝缘膜，形成在第一绝缘膜上并具有细金属颗粒的电荷存储层，形成在电荷存储层上的第二绝缘膜和栅极 电极形成在第二绝缘膜上。 在写入操作期间，在栅极电极和半导体层两端施加差分电压，以使栅极电极位于比半导体层低的电压下，并将正电荷存储在电荷存储层中。

公开(公告)号：US08476708B2

公开(公告)日：2013-07-02

申请号：US13346888

申请日：2012-01-10

申请人： Yoshiaki Fukuzumi ,  Hideaki Aochi ,  Masaru Kito ,  Kiyotaka Miyano ,  Shinji Mori ,  Ichiro Mizushima

发明人： Yoshiaki Fukuzumi ,  Hideaki Aochi ,  Masaru Kito ,  Kiyotaka Miyano ,  Shinji Mori ,  Ichiro Mizushima

IPC分类号： H01L27/01 ,  H01L27/12 ,  H01L31/0392 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L29/792

CPC分类号： H01L27/11582 ,  H01L27/0688 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/1207

摘要： According to one embodiment, a semiconductor memory device includes a semiconductor substrate, memory cell array portion, single-crystal semiconductor layer, and circuit portion. The memory cell array portion is formed on the semiconductor substrate, and includes memory cells. The semiconductor layer is formed on the memory cell array portion, and connected to the semiconductor substrate by being formed in a hole extending through the memory cell array portion.The circuit portion is formed on the semiconductor layer. The Ge concentration in the lower portion of the semiconductor layer is higher than that in the upper portion of the semiconductor layer.

摘要翻译： 根据一个实施例，半导体存储器件包括半导体衬底，存储单元阵列部分，单晶半导体层和电路部分。 存储单元阵列部分形成在半导体衬底上，并且包括存储单元。 半导体层形成在存储单元阵列部分上，并且通过形成在延伸穿过存储单元阵列部分的孔中而连接到半导体衬底。 电路部分形成在半导体层上。 半导体层的下部的Ge浓度高于半导体层的上部的Ge浓度。

公开(公告)号：US20130109157A1

公开(公告)日：2013-05-02

申请号：US13723601

申请日：2012-12-21

申请人： Masaru KITO ,  Yoshiaki FUKUZUMI ,  Masaru KIDOH ,  Megumi ISHIDUKI ,  Yosuke KOMORI ,  Hiroyasu TANAKA ,  Ryota KATSUMATA ,  Hideaki AOCHI

发明人： Masaru KITO ,  Yoshiaki FUKUZUMI ,  Masaru KIDOH ,  Megumi ISHIDUKI ,  Yosuke KOMORI ,  Hiroyasu TANAKA ,  Ryota KATSUMATA ,  Hideaki AOCHI

IPC分类号： H01L29/792

CPC分类号： H01L29/7926 ,  H01L27/0688 ,  H01L27/11551 ,  H01L27/11556 ,  H01L29/7881

摘要： A non-volatile semiconductor storage device includes a plurality of memory strings each having a plurality of electrically rewritable memory cells connected in series. Each of the memory strings comprising: a first semiconductor layer including a columnar portion extending in a vertical direction with respect to a substrate; a plurality of first conductive layers formed to surround side surfaces of the columnar portions via insulation layers, and formed at a certain pitch in the vertical direction, the first conductive layers functioning as floating gates of the memory cells; and a plurality of second conductive layers formed to surround the first conductive layers via insulation layers, and functioning as control electrodes of the memory cells. Each of the first conductive layers has a length in the vertical direction that is shorter than a length in the vertical direction of each of the second conductive layers.

摘要翻译： 非挥发性半导体存储装置包括多个存储串，每个存储串具有串联连接的多个电可重写存储单元。 每个存储器串包括：第一半导体层，包括相对于衬底在垂直方向上延伸的柱状部分; 多个第一导电层，经由绝缘层形成为围绕柱状部分的侧表面，并以垂直方向上的一定间距形成，第一导电层用作存储器单元的浮动栅极; 以及形成为经由绝缘层包围第一导电层并且用作存储单元的控制电极的多个第二导电层。 每个第一导电层在垂直方向上具有比每个第二导电层的垂直方向上的长度短的长度。

公开(公告)号：US08415242B2

公开(公告)日：2013-04-09

申请号：US12886135

申请日：2010-09-20

申请人： Ichiro Mizushima ,  Shinji Mori ,  Yoshiaki Fukuzumi ,  Fumiki Aiso

发明人： Ichiro Mizushima ,  Shinji Mori ,  Yoshiaki Fukuzumi ,  Fumiki Aiso

IPC分类号： H01L21/3205

CPC分类号： H01L29/792 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/7926

摘要： According to one embodiment, a nonvolatile semiconductor memory device is provided in which memory strings, which are formed by providing a plurality of transistors having gate electrode films on sides of columnar semiconductor films in a height direction of the columnar semiconductor films via charge storage layers, are substantially perpendicularly arranged in a matrix shape on a substrate. A coupling section made of a semiconductor material that connects lower portions of the columnar semiconductor films forming a pair of the memory strings adjacent to each other in a predetermined direction is provided. Each of the columnar semiconductor films is formed of a generally single-crystal-like germanium film or silicon germanium film.

公开(公告)号：US20130020627A1

公开(公告)日：2013-01-24

申请号：US13409652

申请日：2012-03-01

申请人： Yoshiaki FUKUZUMI ,  Masaru KITO ,  Tomoko FUJIWARA ,  Kaori KAWASAKI ,  Hideaki AOCHI

发明人： Yoshiaki FUKUZUMI ,  Masaru KITO ,  Tomoko FUJIWARA ,  Kaori KAWASAKI ,  Hideaki AOCHI

IPC分类号： H01L29/788 ,  H01L21/28

CPC分类号： H01L21/84 ,  G11C19/00 ,  H01L27/10 ,  H01L27/11517 ,  H01L27/1203

摘要： In one embodiment, a shift register memory includes first and second control electrodes extending in a first direction parallel to a surface of a substrate, and facing each other in a second direction perpendicular to the first direction. The memory further includes a plurality of first floating electrodes provided in a line on a first control electrode side between the first and second control electrodes. The memory further includes a plurality of second floating electrodes provided in a line on a second control electrode side between the first and second control electrodes. Each of the first and second floating electrodes has a planar shape which is mirror-asymmetric with respect to a plane perpendicular to the first direction.

摘要翻译： 在一个实施例中，移位寄存器存储器包括在平行于衬底表面的第一方向上延伸的第一和第二控制电极，并且在垂直于第一方向的第二方向上彼此面对。 存储器还包括设置在第一和第二控制电极之间的第一控制电极侧的一行中的多个第一浮置电极。 存储器还包括设置在第一和第二控制电极之间的第二控制电极侧的一行中的多个第二浮置电极。 第一和第二浮动电极中的每一个具有相对于垂直于第一方向的平面镜像不对称的平面形状。