公开(公告)号：US20060254348A1

公开(公告)日：2006-11-16

申请号：US11488254

申请日：2006-07-18

申请人： Naoya Watanabe ,  Osamu Takaoka

发明人： Naoya Watanabe ,  Osamu Takaoka

IPC分类号： G01B5/28

CPC分类号： G01Q60/32 ,  G01Q80/00 ,  G03F1/72

摘要： There is provided a device in which a probe can be used for both of observation and correction, and which can, even if a next generation photomask of ultra minute structure is made an object, perform a desired processing without injuring a normal portion in a process of obtaining information of a position and a shape of a defect part, and without impairing the probe also at a processing time. It has been adapted such that, at an observation time, a contact pressure between a probe and a mask is reduced to 0.1 nN by applying a vibration of 1 kHz to 1 MHz to the probe. It has been adapted such that a cantilever used in the present invention is formed by a silicon material of 100-600 μm in length and 5-50 μm in thickness and, at the observation time, the probe contacts with the mask at the contact pressure of 0.1 nN and, at the processing time, a defect correction can be performed by causing the probe to contact with the mask at the contact pressure of 10 nN to 1 mN.

摘要翻译： 提供了一种可以将探头用于观察和校正的装置，并且即使下一代超微小结构的光掩模被制成物体也可以进行所需的处理而不损害处理中的正常部分 获得缺陷部分的位置和形状的信息，并且在处理时间也不损害探针。 已经适应使得在观察时间，通过向探针施加1kHz至1MHz的振动，将探针和掩模之间的接触压力降低至0.1nN。 已经适应使得本发明中使用的悬臂由长度为100〜600μm，厚度为5-50μm的硅材料形成，并且在观察时刻，探针以接触压力与掩模接触 0.1nN，并且在处理时间，可以通过使探针以10nN至1mN的接触压力与掩模接触来进行缺陷校正。

公开(公告)号：US07130064B1

公开(公告)日：2006-10-31

申请号：US09598201

申请日：2000-06-21

申请人： Koji Okamura ,  Naoya Watanabe

发明人： Koji Okamura ,  Naoya Watanabe

IPC分类号： G06F15/00

CPC分类号： H04N1/56

摘要： An image processing system includes an input unit, a selecting unit, a determining unit and a control unit. The input unit inputs one of a color image and a monochrome image, and the selecting unit selects either a normal recording mode for recording an image on a recording material at a predetermined recording density, and a decimation recording mode for recording the image on the recording material at a recording density lower than that of the normal recording mode. The determining unit determines if the input image is a color image or a monochrome image, and the control unit changes to the normal recording mode, when the decimation recording mode is selected and the input image is determined to be a color image.

摘要翻译： 图像处理系统包括输入单元，选择单元，确定单元和控制单元。 输入单元输入彩色图像和单色图像之一，并且选择单元以预定的记录密度选择用于在记录材料上记录图像的正常记录模式，以及用于在记录上记录图像的抽取记录模式 材料的记录密度低于正常记录模式。 当选择抽取记录模式并将输入图像确定为彩色图像时，确定单元确定输入图像是彩色图像还是单色图像，并且控制单元改变为正常记录模式。

公开(公告)号：US06770188B2

公开(公告)日：2004-08-03

申请号：US10045563

申请日：2002-01-11

申请人： Masayuki Suda ,  Naoya Watanabe ,  Kazuyoshi Furuta

发明人： Masayuki Suda ,  Naoya Watanabe ,  Kazuyoshi Furuta

IPC分类号： B23H1100

CPC分类号： B23H9/00

摘要： A structural body material layer is formed directly on a base substrate or via a sacrificing layer or a peeling layer, a groove is fabricated electrochemically along an outer configuration shape of a part constituting an object at the structural body material layer and thereafter, only the sacrificing layer or the base substrate is selectively removed or the part is mechanically separated from the peeling layer to thereby separate the part and the base substrate and provide the part constituting the object or fabricate a part having a movable portion by partially restricting a portion to be separated.

摘要翻译： 结构体材料层直接形成在基底基板上，或通过牺牲层或剥离层形成，沿构造物体在构造体材料层的外部构造形状电化学地制造凹槽，然后仅牺牲 选择性地去除层或基底，或者将部分与剥离层机械分离，从而分离部件和基底，并且通过部分地限制待分离的部分来提供构成物体的部分或制造具有可移动部分的部分 。

公开(公告)号：US6160434A

公开(公告)日：2000-12-12

申请号：US177379

申请日：1998-10-23

申请人： Tsutomu Yoshimura ,  Yasunobu Nakase ,  Yoshikazu Morooka ,  Naoya Watanabe

发明人： Tsutomu Yoshimura ,  Yasunobu Nakase ,  Yoshikazu Morooka ,  Naoya Watanabe

IPC分类号： H03K5/00 ,  H03K5/13

CPC分类号： H03K5/133 ,  H03K2005/00039 ,  H03K2005/00286

摘要： Transistors (MP1 and MP2) supply a current (I.sub.0) for nodes (K and L), respectively. Transistors (MN10 and MN11) draw the same current from nodes (K and L), respectively. A parallel connection of serial connections (N1 and N2) draws a current (I.sub.1) from the node (K) only when an exclusive OR of clocks (S1 and S2) is "H". On the other hand, a parallel connection of serial connections (N3 and N4) draws a current (I.sub.1) from the node (L) only when the exclusive OR of clocks (S1 and S2) is "L". When the current (I.sub.1) is drawn from the node (K), the current (I.sub.1) flows out from the node (L) and when the current (I.sub.1) is drawn from the node (L), the current (I.sub.1) flows into the node (L). In the serial connections (N1 to N4), each of the clocks (S1 and S2) and their inverted signals (S1B and S2B) is applied to one of the gates of the transistors (MN1 to MN8) and therefore a uniform input load is obtained. With this configuration provided is a 90-degree phase shifter which achieves the uniform input load to improve a phase offset.

摘要翻译： 晶体管（MP1和MP2）分别为节点（K和L）提供电流（I0）。 晶体管（MN10和MN11）分别从节点（K和L）绘出相同的电流。 串行连接（N1和N2）的并联连接仅在时钟（S1和S2）的异或“为”H“时从节点（K）抽出电流（I1）。 另一方面，仅当时钟（S1和S2）的异或为“L”时，串行连接（N3和N4）的并联连接从节点（L）抽出电流（I1）。 当从节点（K）抽出电流（I1）时，电流（I1）从节点（L）流出，当电流（I1）从节点（L）抽出时，电流（I1）流 进入节点（L）。 在串行连接（N1〜N4）中，每个时钟（S1和S2）及其反相信号（S1B和S2B）被施加到晶体管（MN1至MN8）的一个栅极，因此均匀的输入负载 获得。 所提供的这种配置是实现均匀输入负载以提高相位偏移的90度移相器。

公开(公告)号：US6101151A

公开(公告)日：2000-08-08

申请号：US196245

申请日：1998-11-20

申请人： Naoya Watanabe ,  Yoshikazu Morooka ,  Tsutomu Yoshimura ,  Yasunobu Nakase

发明人： Naoya Watanabe ,  Yoshikazu Morooka ,  Tsutomu Yoshimura ,  Yasunobu Nakase

IPC分类号： G11C11/413 ,  G11C7/00 ,  G11C7/10 ,  G11C7/22 ,  G11C11/407 ,  G11C11/409 ,  G11C8/00

CPC分类号： G11C7/22 ,  G11C7/1051 ,  G11C7/1072

摘要： In a synchronous semiconductor memory device in which an internal clock signal from an internal timing clock signal generating circuit is branched in the form of a tree by driver circuits and applied to output buffers and data are output in synchronization with the internal clock signal, the driver circuit of the first stage is constituted by an NAND gate and an inverter. When output is to be temporarily stopped, an enabling signal is set to "L" level, so that the NAND gate is closed, output of the clock signal to each driver circuit is stopped, and thus power consumption is reduced.

摘要翻译： 在同步半导体存储器件中，来自内部定时时钟信号产生电路的内部时钟信号以树形式被驱动电路分支并且被施加到输出缓冲器和数据与内部时钟信号同步输出， 第一级的电路由NAND门和反相器构成。 当暂时停止输出时，使能信号被设置为“L”电平，使得与非门关闭，从而停止对每个驱动电路的时钟信号的输出，从而降低功耗。

公开(公告)号：US6091659A

公开(公告)日：2000-07-18

申请号：US318433

申请日：1999-05-25

申请人： Naoya Watanabe ,  Katsumi Dosaka

发明人： Naoya Watanabe ,  Katsumi Dosaka

IPC分类号： G11C11/407 ,  G11C7/10 ,  G11C8/16 ,  G11C11/401 ,  G11C11/409 ,  G11C8/00

CPC分类号： G11C8/16 ,  G11C7/1006

摘要： Memory blocks provided to share a sense amplifier band, a global IO (GIOB) bus provided in common to the memory blocks for transferring internal data, and local IO bus lines provided corresponding to the memory blocks are connection-controlled based on signals related to a column select operation. Driving memory blocks independently from each other permits each memory block to be used as a bank, and if one memory block is accessed during activation of another memory block, data can be prevented from colliding on the global IO bus. A main memory with high page hit rate is implemented using a semiconductor memory device with a shared-sense amplifier configuration. When a memory block sharing a sense amplifier coupled to another memory block is addressed, the another memory block is inactivated and then addressed memory block is accessed, when a valid data is output, such valid data outputting is signaled by a data valid signal.

摘要翻译： 提供用于共享读出放大器频带的存储器块，共同提供用于传送内部数据的存储器块的全局IO（GIOB）总线以及与存储器块相对应地提供的本地IO总线的连接控制是基于与 列选择操作。 彼此独立地驱动存储器块允许每个存储器块用作存储体，并且如果在激活另一个存储器块期间访问一个存储器块，则可以防止数据在全局IO总线上冲突。 具有高页命中率的主存储器使用具有共享读出放大器配置的半导体存储器件来实现。 当共享耦合到另一个存储器块的读出放大器的存储器块被寻址时，另一个存储块被去激活，然后寻址存储器块被访问，当输出有效数据时，这样的有效数据输出由数据有效信号发出。

公开(公告)号：US5963502A

公开(公告)日：1999-10-05

申请号：US112439

申请日：1998-07-09

申请人： Naoya Watanabe ,  Yoshikazu Morooka ,  Tsutomu Yoshimura ,  Yasunobu Nakase

发明人： Naoya Watanabe ,  Yoshikazu Morooka ,  Tsutomu Yoshimura ,  Yasunobu Nakase

IPC分类号： G11C11/413 ,  G11C7/10 ,  G11C7/22 ,  G11C11/407 ,  G11C11/409 ,  H03L7/06 ,  G11C7/00

CPC分类号： G11C7/22 ,  G11C7/1072

摘要： A voltage controlled delay circuit having the same structure, except for a loop, as a voltage controlled oscillator included in a PLL circuit which in turn generates an internal clock signal from an external clock signal is controlled by a control voltage from the PLL circuit, and the delay output of the voltage controlled delay circuit is selected by a selection circuit in accordance with the output signal of a vernier-adjusting counter in order to generate a read clock signal. Therefore, a vernier for optimizing data input timing in a controller can be realized which always has a constant delay amount regardless of a change in operating environment.

摘要翻译： 作为包括在PLL电路中的压控振荡器，具有与循环不同的结构的电压控制延迟电路，该PLL电路又由外部时钟信号产生内部时钟信号，由PLL电路的控制电压控制， 电压控制延迟电路的延迟输出由选择电路根据游标调节计数器的输出信号选择，以产生读时钟信号。 因此，可以实现用于优化控制器中的数据输入定时的游标，其总是具有恒定的延迟量，而与操作环境的变化无关。

公开(公告)号：US5956349A

公开(公告)日：1999-09-21

申请号：US781248

申请日：1997-01-10

申请人： Naoya Watanabe ,  Akira Yamazaki

发明人： Naoya Watanabe ,  Akira Yamazaki

IPC分类号： G06F11/08 ,  G06F12/06 ,  G11C11/401 ,  G11C11/407 ,  G11C29/00 ,  G11C29/12 ,  G11C29/14 ,  G11C29/44 ,  G11C29/48

CPC分类号： G11C29/48 ,  G11C29/14 ,  G11C29/44

摘要： A memory includes a built-in testing circuit for determining pass/fail of a memory portion and an identifier register for storing identification value for identifying the memory. The memory performs a testing operation according to a command provided from a controller via a send link and sends the result of that testing to a sync link. Thus, the memory controller can identify a defective memory cell. In this way, erroneous operation of the system due to a defective memory cell in a memory system can be prevented.

摘要翻译： 存储器包括用于确定存储器部分的通过/失败的内置测试电路和用于存储用于识别存储器的识别值的标识符寄存器。 存储器根据从控制器经由发送链路提供的命令执行测试操作，并将该测试的结果发送到同步链路。 因此，存储器控制器可以识别有缺陷的存储器单元。 以这种方式，可以防止由于存储器系统中的缺陷存储器单元导致的系统的错误操作。

公开(公告)号：US5689289A

公开(公告)日：1997-11-18

申请号：US348223

申请日：1994-11-28

申请人： Naoya Watanabe ,  Makoto Kobayashi ,  Junji Iguchi ,  Yasuyuki Shinada ,  Yukio Nohata ,  Yuji Shimahara

发明人： Naoya Watanabe ,  Makoto Kobayashi ,  Junji Iguchi ,  Yasuyuki Shinada ,  Yukio Nohata ,  Yuji Shimahara

IPC分类号： B41J2/175 ,  B41J11/46 ,  B41J29/393 ,  B41J2/195 ,  B41J2/205

CPC分类号： B41J29/393 ,  B41J11/46 ,  B41J2/17566

摘要： A standard print mode or a thinning print mode can be selected at will by an input from an operation panel to record image data received by a receiving means section in a selected print mode using an ink jet recording head, And after one page of image recording, a footer mark is recorded on the trailing portion of the recording paper, and sensed by a photo sensor to determine whether or not the ink is present. This footer mark is recorded in the standard print mode without regard to the selected print mode. Thereby, the false detection of the predetermined image recorded on the recording medium, after a predefined amount of image data has been recorded, can be prevented.

摘要翻译： 可以通过来自操作面板的输入随意选择标准打印模式或间隔打印模式，以使用喷墨记录头在所选择的打印模式中记录由接收装置部分接收的图像数据，并且在一页图像记录之后 在记录纸的尾部记录有脚印标记，并由光传感器感测，以确定是否存在墨。 这种页脚标记以标准打印模式记录，而不考虑所选的打印模式。 因此，可以防止在记录了预定量的图像数据之后记录在记录介质上的预定图像的错误检测。

公开(公告)号：US08866700B2

公开(公告)日：2014-10-21

申请号：US13456528

申请日：2012-04-26

申请人： Akiko Inami ,  Naoya Watanabe

发明人： Akiko Inami ,  Naoya Watanabe

IPC分类号： G09G5/00 ,  G06F1/16

CPC分类号： G06F3/041 ,  G06F1/1616 ,  G06F1/1624 ,  G06F1/1641 ,  G06F3/0488 ,  G06F3/1423 ,  G06F3/1438 ,  G06F2200/1637 ,  G09G5/00 ,  G09G5/39 ,  G09G2300/02 ,  G09G2330/02 ,  G09G2360/127

摘要： A first cabinet comprising a first display module and a second cabinet comprising a second display module are provided. A switching is allowed between: a first state in which the first cabinet is placed on top of the second display module and the first display module faces outside, and a second state in which the first cabinet and the second cabinet are arranged next to each other and the first display module and the second display module face outside. A first screen to be displayed by the first display module and a second screen to be displayed by the second display module are stored and a screen switching operation is detected. Displaying of the first screen on the first display module is canceled and the second screen is displayed on the first display module, when the screen switching operation is detected in the first state.

摘要翻译： 提供了包括第一显示模块和包括第二显示模块的第二机柜的第一机柜。 允许在以下情况之间进行切换：其中第一机柜放置在第二显示模块的顶部上的第一状态和第一显示模块面向外部;第二状态，其中第一机柜和第二机柜彼此相邻布置 并且第一显示模块和第二显示模块面向外部。 存储由第一显示模块显示的第一屏幕和由第二显示模块显示的第二屏幕，并且检测屏幕切换操作。 当在第一状态下检测到屏幕切换操作时，第一显示模块上的第一屏幕的显示被取消，第二屏幕显示在第一显示模块上。