摘要:
A nitrile group-containing highly saturated copolymer rubber having α,β-ethylenically unsaturated nitrile monomer units (a) and conjugated diene monomer units (b) and having at least part of said conjugated diene monomer units (b) hydrogenated, wherein a content of said α,β-ethylenically unsaturated nitrile monomer units (a) is 37 to 45 wt %, a total of said α,β-ethylenically unsaturated nitrile monomer units (a) and said conjugated diene monomer units (b) is 93 wt % or more, an iodine value is 9 or less, and a half value width of a peak of a loss tangent (tanδ) in the viscoelastic properties when made into a cross-linked product is 5 to 20° C. in range.
摘要:
A frequency comparator detects the phase of a data signal DATA by using four-phase clocks ICLK, /ICLK, QCLK and /QCLK as a reference and detects a change in the phase. A counting processing unit counts a period in which a control signal UP2 or DN2 is activated within a predetermined period, and outputs an overflow detection signal LOL2 if the frequency is high. A hysteresis generating unit changes a signal LOL to the L level only after signal LOL goes low X times consecutively. On the other hand, after signal LOL is set to the L level once, the hysteresis generating unit changes signal LOL to the H level only after signal LOL2 goes high X times consecutively. With such a configuration, a phase-locked state detecting circuit with reduced malfunction even when a data signal having larger jitter is input can be provided.
摘要:
Transistors (MP1 and MP2) supply a current (I.sub.0) for nodes (K and L), respectively. Transistors (MN10 and MN11) draw the same current from nodes (K and L), respectively. A parallel connection of serial connections (N1 and N2) draws a current (I.sub.1) from the node (K) only when an exclusive OR of clocks (S1 and S2) is "H". On the other hand, a parallel connection of serial connections (N3 and N4) draws a current (I.sub.1) from the node (L) only when the exclusive OR of clocks (S1 and S2) is "L". When the current (I.sub.1) is drawn from the node (K), the current (I.sub.1) flows out from the node (L) and when the current (I.sub.1) is drawn from the node (L), the current (I.sub.1) flows into the node (L). In the serial connections (N1 to N4), each of the clocks (S1 and S2) and their inverted signals (S1B and S2B) is applied to one of the gates of the transistors (MN1 to MN8) and therefore a uniform input load is obtained. With this configuration provided is a 90-degree phase shifter which achieves the uniform input load to improve a phase offset.
摘要:
In a synchronous semiconductor memory device in which an internal clock signal from an internal timing clock signal generating circuit is branched in the form of a tree by driver circuits and applied to output buffers and data are output in synchronization with the internal clock signal, the driver circuit of the first stage is constituted by an NAND gate and an inverter. When output is to be temporarily stopped, an enabling signal is set to "L" level, so that the NAND gate is closed, output of the clock signal to each driver circuit is stopped, and thus power consumption is reduced.
摘要:
A voltage controlled delay circuit having the same structure, except for a loop, as a voltage controlled oscillator included in a PLL circuit which in turn generates an internal clock signal from an external clock signal is controlled by a control voltage from the PLL circuit, and the delay output of the voltage controlled delay circuit is selected by a selection circuit in accordance with the output signal of a vernier-adjusting counter in order to generate a read clock signal. Therefore, a vernier for optimizing data input timing in a controller can be realized which always has a constant delay amount regardless of a change in operating environment.
摘要:
A glycerin derivative having the following formula (I) or (I') and a pharmacologically acceptable salt thereof are useful to treat diseases caused by the platelet activating factor. ##STR1##
摘要:
A glycerin derivative having the following formula (I) or (I') and a pharmacologically acceptable salt thereof are useful to treat diseases caused by the platelet activating factor. ##STR1##
摘要:
An amplifier circuit includes a first differential amplifier circuit, a second differential amplifier circuit which amplifies an output signal from the first differential amplifier circuit, and an active feedback circuit which performs waveform shaping on the output signal from the first differential amplifier circuit by feeding back an output signal from the second differential amplifier circuit. The active feedback circuit includes first and second transistors having collectors or drains respectively connected to respective output nodes of the first differential amplifier circuit, bases or gates respectively connected to two output nodes of the second differential amplifier circuit, and emitters or sources connected in common, and a first current source which has a first end connected to the emitters or sources of the first and second transistors, and a second end connected to a low-voltage power supply, and producing a current that can be externally adjusted.
摘要:
An automatic frequency correction phase-locked loop (PLL) circuit includes an analog control circuit and a digital control circuit. The digital control circuit includes a High-side comparator and a Low-side comparator which receive an analog control voltage, a state monitor circuit, and a counter and decoder circuit. At least one of the High-side comparator and the Low-side comparator includes a threshold switching circuit which selectively gives a first threshold and a second threshold having different. When the analog control voltage remains between the High-side threshold and the Low-side threshold in a state in which the threshold switching circuit gives the first threshold, the threshold switching circuit switches the first threshold to the second threshold and expands the interval between the High-side threshold and the Low-side threshold.
摘要:
A signal according to a phase difference in a first phase-locked loop is transferred to a power supply line as an operation power supply voltage for a first oscillation circuit included in the first phase-locked loop. The potential of the power supply line is supplied to a second oscillation circuit in a second phase-locked loop as an operation power supply voltage. The second phase-locked loop is used to generate a clock signal phase-synchronized to the input clock signal. Consequently, a clock generator is implemented that oscillates at a central frequency to generate a recovered clock signal even when a variation is caused in a manufacturing parameter.