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    Ninety-degree phase shifter
    1.
    发明授权
    Ninety-degree phase shifter 失效
    九十度移相器

    公开(公告)号：US6160434A

    公开(公告)日：2000-12-12

    申请号：US177379

    申请日：1998-10-23

    申请人： Tsutomu Yoshimura ,  Yasunobu Nakase ,  Yoshikazu Morooka ,  Naoya Watanabe

    发明人： Tsutomu Yoshimura ,  Yasunobu Nakase ,  Yoshikazu Morooka ,  Naoya Watanabe

    IPC分类号： H03K5/00 ,  H03K5/13

    CPC分类号： H03K5/133 ,  H03K2005/00039 ,  H03K2005/00286

    摘要： Transistors (MP1 and MP2) supply a current (I.sub.0) for nodes (K and L), respectively. Transistors (MN10 and MN11) draw the same current from nodes (K and L), respectively. A parallel connection of serial connections (N1 and N2) draws a current (I.sub.1) from the node (K) only when an exclusive OR of clocks (S1 and S2) is "H". On the other hand, a parallel connection of serial connections (N3 and N4) draws a current (I.sub.1) from the node (L) only when the exclusive OR of clocks (S1 and S2) is "L". When the current (I.sub.1) is drawn from the node (K), the current (I.sub.1) flows out from the node (L) and when the current (I.sub.1) is drawn from the node (L), the current (I.sub.1) flows into the node (L). In the serial connections (N1 to N4), each of the clocks (S1 and S2) and their inverted signals (S1B and S2B) is applied to one of the gates of the transistors (MN1 to MN8) and therefore a uniform input load is obtained. With this configuration provided is a 90-degree phase shifter which achieves the uniform input load to improve a phase offset.

    摘要翻译： 晶体管（MP1和MP2）分别为节点（K和L）提供电流（I0）。 晶体管（MN10和MN11）分别从节点（K和L）绘出相同的电流。 串行连接（N1和N2）的并联连接仅在时钟（S1和S2）的异或“为”H“时从节点（K）抽出电流（I1）。 另一方面，仅当时钟（S1和S2）的异或为“L”时，串行连接（N3和N4）的并联连接从节点（L）抽出电流（I1）。 当从节点（K）抽出电流（I1）时，电流（I1）从节点（L）流出，当电流（I1）从节点（L）抽出时，电流（I1）流 进入节点（L）。 在串行连接（N1〜N4）中，每个时钟（S1和S2）及其反相信号（S1B和S2B）被施加到晶体管（MN1至MN8）的一个栅极，因此均匀的输入负载 获得。 所提供的这种配置是实现均匀输入负载以提高相位偏移的90度移相器。

    Synchronous semiconductor memory device employing temporary data output stop scheme
    2.
    发明授权
    Synchronous semiconductor memory device employing temporary data output stop scheme 失效
    采用临时数据输出停止方案的同步半导体存储器件

    公开(公告)号：US6101151A

    公开(公告)日：2000-08-08

    申请号：US196245

    申请日：1998-11-20

    申请人： Naoya Watanabe ,  Yoshikazu Morooka ,  Tsutomu Yoshimura ,  Yasunobu Nakase

    发明人： Naoya Watanabe ,  Yoshikazu Morooka ,  Tsutomu Yoshimura ,  Yasunobu Nakase

    IPC分类号： G11C11/413 ,  G11C7/00 ,  G11C7/10 ,  G11C7/22 ,  G11C11/407 ,  G11C11/409 ,  G11C8/00

    CPC分类号： G11C7/22 ,  G11C7/1051 ,  G11C7/1072

    摘要： In a synchronous semiconductor memory device in which an internal clock signal from an internal timing clock signal generating circuit is branched in the form of a tree by driver circuits and applied to output buffers and data are output in synchronization with the internal clock signal, the driver circuit of the first stage is constituted by an NAND gate and an inverter. When output is to be temporarily stopped, an enabling signal is set to "L" level, so that the NAND gate is closed, output of the clock signal to each driver circuit is stopped, and thus power consumption is reduced.

    摘要翻译： 在同步半导体存储器件中，来自内部定时时钟信号产生电路的内部时钟信号以树形式被驱动电路分支并且被施加到输出缓冲器和数据与内部时钟信号同步输出， 第一级的电路由NAND门和反相器构成。 当暂时停止输出时，使能信号被设置为“L”电平，使得与非门关闭，从而停止对每个驱动电路的时钟信号的输出，从而降低功耗。

    Clock-synchronous type semiconductor memory device capable of outputting read clock signal at correct timing
    3.
    发明授权
    Clock-synchronous type semiconductor memory device capable of outputting read clock signal at correct timing 失效
    时钟同步型半导体存储器件能够以正确的时序输出读时钟信号

    公开(公告)号：US5963502A

    公开(公告)日：1999-10-05

    申请号：US112439

    申请日：1998-07-09

    申请人： Naoya Watanabe ,  Yoshikazu Morooka ,  Tsutomu Yoshimura ,  Yasunobu Nakase

    发明人： Naoya Watanabe ,  Yoshikazu Morooka ,  Tsutomu Yoshimura ,  Yasunobu Nakase

    IPC分类号： G11C11/413 ,  G11C7/10 ,  G11C7/22 ,  G11C11/407 ,  G11C11/409 ,  H03L7/06 ,  G11C7/00

    CPC分类号： G11C7/22 ,  G11C7/1072

    摘要： A voltage controlled delay circuit having the same structure, except for a loop, as a voltage controlled oscillator included in a PLL circuit which in turn generates an internal clock signal from an external clock signal is controlled by a control voltage from the PLL circuit, and the delay output of the voltage controlled delay circuit is selected by a selection circuit in accordance with the output signal of a vernier-adjusting counter in order to generate a read clock signal. Therefore, a vernier for optimizing data input timing in a controller can be realized which always has a constant delay amount regardless of a change in operating environment.

    摘要翻译： 作为包括在PLL电路中的压控振荡器，具有与循环不同的结构的电压控制延迟电路，该PLL电路又由外部时钟信号产生内部时钟信号，由PLL电路的控制电压控制， 电压控制延迟电路的延迟输出由选择电路根据游标调节计数器的输出信号选择，以产生读时钟信号。 因此，可以实现用于优化控制器中的数据输入定时的游标，其总是具有恒定的延迟量，而与操作环境的变化无关。

    Circuit module
    4.
    发明授权
    Circuit module 失效
    电路模块

    公开(公告)号：US06392897B1

    公开(公告)日：2002-05-21

    申请号：US09131688

    申请日：1998-08-10

    申请人： Yasunobu Nakase ,  Tsutomu Yoshimura ,  Yoshikazu Morooka ,  Naoya Watanabe

    发明人： Yasunobu Nakase ,  Tsutomu Yoshimura ,  Yoshikazu Morooka ,  Naoya Watanabe

    IPC分类号： H01R1216

    CPC分类号： H05K1/14 ,  H05K1/117 ,  H05K3/403 ,  H05K2201/09481 ,  H05K2201/10159 ,  H05K2201/10689 ,  H05K2203/1572

    摘要： A circuit module includes a connector terminal (4A) provided on a front surface of a printed wiring board (2) and connected to a data pin (DQt) of a memory IC (3) through an interconnect line (5a). A conductive connector terminal (4c) corresponds to the connector terminal (4a) and is provided on a back surface of the printed wiring board (2). A through hole (16) extends between part of the front surface of the printed wiring board (2) where the connector terminal (4a) is formed and part of the back surface thereof where the conductive connector terminal (4c) is formed. A conductor fills the through hole (16), thereby suppressing skews resulting from a difference in interconnect line length on the circuit module and decreasing a stub capacitance to achieve the reduction in power consumption.

    摘要翻译： 电路模块包括设置在印刷电路板（2）的前表面并通过互连线（5a）连接到存储器IC（3）的数据引脚（DQt）的连接器端子（4A）。 导电连接器端子（4c）对应于连接器端子（4a）并且设置在印刷电路板（2）的背面上。 在形成有连接器端子（4a）的印刷电路板（2）的前表面的一部分和形成导电连接器端子（4c）的背面的一部分之间延伸有一个通孔（16）。 导体填充通孔（16），从而抑制由电路模块上的互连线长度的差异引起的偏移，并且减小短截线电容以实现功耗的降低。

    Delay locked loop circuit
    5.
    发明授权
    Delay locked loop circuit 失效
    延时锁定回路电路

    公开(公告)号：US5994934A

    公开(公告)日：1999-11-30

    申请号：US111875

    申请日：1998-07-08

    申请人： Tsutomu Yoshimura ,  Yasunobu Nakase ,  Yoshikazu Morooka ,  Naoya Watanabe ,  Harufusa Kondoh ,  Hiromi Notani

    发明人： Tsutomu Yoshimura ,  Yasunobu Nakase ,  Yoshikazu Morooka ,  Naoya Watanabe ,  Harufusa Kondoh ,  Hiromi Notani

    IPC分类号： G06F1/10 ,  G11C11/4076 ,  H03K5/00 ,  H03K5/13 ,  H03K5/131 ,  H03L7/00 ,  H03L7/081 ,  H03L7/089 ,  H03L7/095 ,  H03L7/06

    CPC分类号： H03L7/0812 ,  H03L7/0891 ,  H03L7/095

    摘要： Provided is a DLL circuit that can execute a precise delay synchronization operation without increasing the variable delay time range of a delay line. The DLL circuit comprises a phase comparator (3), a charge pump (6), an LPF (8) and a delay line (9), and operates to match phases of an input signal (CLKIN) and a feedback signal (FBCLK). The phase comparator (3) always outputs a phase comparison result that causes a delay time of the delay line (9) to increase, at the time of initial operation after a reset operation. The LPF (8) outputs a delay adjusting signal (S8) indicating that a delay time due to the delay line (9) becomes the minimum, in executing a reset.

    摘要翻译： 提供了可以在不增加延迟线的可变延迟时间范围的情况下执行精确的延迟同步操作的DLL电路。 DLL电路包括相位比较器（3），电荷泵（6），LPF（8）和延迟线（9），并且操作以匹配输入信号（CLKIN）和反馈信号（FBCLK）的相位， 。 相位比较器（3）总是输出在复位操作之后的初始操作时延迟线（9）的延迟时间增加的相位比较结果。 在执行复位时，LPF（8）输出指示由于延迟线（9）引起的延迟时间变为最小的延迟调整信号（S8）。

    NITRILE GROUP-CONTAINING HIGHLY SATURATED COPOLYMER RUBBER
    6.
    发明申请
    NITRILE GROUP-CONTAINING HIGHLY SATURATED COPOLYMER RUBBER 审中-公开
    含有高分子量饱和的共聚物橡胶

    公开(公告)号：US20110105692A1

    公开(公告)日：2011-05-05

    申请号：US13001561

    申请日：2009-06-26

    申请人： Tsutomu Yoshimura ,  Kiyonori Umetsu ,  Shinya Ikeda

    发明人： Tsutomu Yoshimura ,  Kiyonori Umetsu ,  Shinya Ikeda

    IPC分类号： C08F8/04

    CPC分类号： C08C19/02 ,  C08F236/12 ,  C08K5/14 ,  C08F2/001 ,  C08L15/005

    摘要： A nitrile group-containing highly saturated copolymer rubber having α,β-ethylenically unsaturated nitrile monomer units (a) and conjugated diene monomer units (b) and having at least part of said conjugated diene monomer units (b) hydrogenated, wherein a content of said α,β-ethylenically unsaturated nitrile monomer units (a) is 37 to 45 wt %, a total of said α,β-ethylenically unsaturated nitrile monomer units (a) and said conjugated diene monomer units (b) is 93 wt % or more, an iodine value is 9 or less, and a half value width of a peak of a loss tangent (tanδ) in the viscoelastic properties when made into a cross-linked product is 5 to 20° C. in range.

    摘要翻译： 具有α，b-烯属不饱和腈单体单元（a）和共轭二烯单体单元（b）并且具有至少部分所述共轭二烯单体单元（b）的含腈基的高度饱和的共聚物橡胶被氢化，其中含量 的所述α，β-烯键式不饱和腈单体单元（a）的含量为37〜45重量％，所述α，b-烯属不饱和腈单体单元（a）和所述共轭二烯单体单元（b）的总和为93 重量％以上，碘值为9以下，制成交联体时的粘弹性的损耗角正切（tanδ）的峰值的半值宽度为5〜20℃。

    Frequency comparator with malfunction reduced and phase-locked state detecting circuit using the same
    7.
    发明授权
    Frequency comparator with malfunction reduced and phase-locked state detecting circuit using the same 失效
    频率比较器故障降低，锁相状态检测电路采用相同方式

    公开(公告)号：US06707319B2

    公开(公告)日：2004-03-16

    申请号：US10327864

    申请日：2002-12-26

    申请人： Tsutomu Yoshimura

    发明人： Tsutomu Yoshimura

    IPC分类号： G01R2500

    CPC分类号： H03D13/004

    摘要： A frequency comparator detects the phase of a data signal DATA by using four-phase clocks ICLK, /ICLK, QCLK and /QCLK as a reference and detects a change in the phase. A counting processing unit counts a period in which a control signal UP2 or DN2 is activated within a predetermined period, and outputs an overflow detection signal LOL2 if the frequency is high. A hysteresis generating unit changes a signal LOL to the L level only after signal LOL goes low X times consecutively. On the other hand, after signal LOL is set to the L level once, the hysteresis generating unit changes signal LOL to the H level only after signal LOL2 goes high X times consecutively. With such a configuration, a phase-locked state detecting circuit with reduced malfunction even when a data signal having larger jitter is input can be provided.

    摘要翻译： 频率比较器通过使用四相时钟ICLK，/ ICLK，QCLK和/ QCLK作为参考来检测数据信号DATA的相位，并检测相位的变化。 计数处理单元计算在预定时间段内控制信号UP2或DN2被激活的时段，并且如果频率高，则输出溢出检测信号LOL2。 迟滞发生单元仅在信号LOL连续低X次后将信号LOL改变为L电平。 另一方面，在信号LOL被设置为L电平一次之后，滞后发生单元仅在信号LOL2连续变高X次之后才将信号LOL改变为H电平。 通过这样的结构，即使输入了具有较大抖动的数据信号，也能够提供具有降低的故障的锁相状态检测电路。

    Amplifier circuit
    10.
    发明授权
    Amplifier circuit 有权
    放大器电路

    公开(公告)号：US07295072B2

    公开(公告)日：2007-11-13

    申请号：US11197376

    申请日：2005-08-05

    申请人： Jun Takaso ,  Tsutomu Yoshimura ,  Norio Higashisaka

    发明人： Jun Takaso ,  Tsutomu Yoshimura ,  Norio Higashisaka

    IPC分类号： H03F3/45

    CPC分类号： H03F3/45085 ,  H03F2203/45631 ,  H03F2203/45652 ,  H03F2203/45702

    摘要： An amplifier circuit includes a first differential amplifier circuit, a second differential amplifier circuit which amplifies an output signal from the first differential amplifier circuit, and an active feedback circuit which performs waveform shaping on the output signal from the first differential amplifier circuit by feeding back an output signal from the second differential amplifier circuit. The active feedback circuit includes first and second transistors having collectors or drains respectively connected to respective output nodes of the first differential amplifier circuit, bases or gates respectively connected to two output nodes of the second differential amplifier circuit, and emitters or sources connected in common, and a first current source which has a first end connected to the emitters or sources of the first and second transistors, and a second end connected to a low-voltage power supply, and producing a current that can be externally adjusted.

    摘要翻译： 放大器电路包括：第一差分放大器电路，放大来自第一差分放大器电路的输出信号的第二差分放大器电路;以及有源反馈电路，其对来自第一差分放大器电路的输出信号进行波形整形， 来自第二差分放大器电路的输出信号。 有源反馈电路包括具有分别连接到第一差分放大器电路的相应输出节点的收集器或漏极的第一和第二晶体管，分别连接到第二差分放大器电路的两个输出节点的基极或门，以及共同连接的发射器或源， 以及第一电流源，其具有连接到第一和第二晶体管的发射极或源极的第一端，以及连接到低压电源的第二端，并且产生可以从外部调节的电流。