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公开(公告)号：US20190068316A1
公开(公告)日：2019-02-28
申请号：US16163169
申请日：2018-10-17
Applicant: Huawei Technologies Co., Ltd.
Inventor： Huazi Zhang , Jiajie Tong , Rong Li , Jun Wang , Wen Tong , Yiqun Ge , Xiaocheng Liu , Gongzheng Zhang , Jian Wang , Nan Cheng , Qifan Zhang
Abstract: Embodiment techniques map parity bits to sub-channels based on their row weights. In one example, an embodiment technique includes polar encoding, with an encoder of the device, information bits and at least one parity bit using the polar code to obtain encoded data, and transmitting the encoded data to another device. The polar code comprises a plurality of sub-channels. The at least one parity bit being placed in at least one of the plurality of sub-channels. The at least one sub-channel is selected from the plurality of sub-channels based on a weight parameter.
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Patent Agency Ranking
12.发明授权公开(公告)号：US10042641B2
公开(公告)日：2018-08-07
申请号：US14480573
申请日：2014-09-08
Applicant: Huawei Technologies Co. Ltd
Inventor： Qifan Zhang , Wuxian Shi , Yiqun Ge , Tao Huang , Wen Tong
Abstract: An asynchronous processing system comprising an asynchronous scalar processor and an asynchronous vector processor coupled to the scalar processor. The asynchronous scalar processor is configured to perform processing functions on input data and to output instructions. The asynchronous vector processor is configured to perform processing functions in response to a very long instruction word (VLIW) received from the scalar processor. The VLIW comprises a first portion and a second portion, at least the first portion comprising a vector instruction.
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公开(公告)号：US20180076929A1
公开(公告)日：2018-03-15
申请号：US15699976
申请日：2017-09-08
Applicant: Huawei Technologies Co., Ltd.
Inventor： Huazi Zhang , Jiajie Tong , Rong Li , Jun Wang , Wen Tong , Yiqun Ge , Xiaocheng Liu , Gongzheng Zhang , Jian Wang , Nan Cheng , Qifan Zhang
CPC classification number: H04L1/0009 , H03M13/11 , H03M13/13 , H03M13/611 , H03M13/616 , H03M13/6362 , H04L1/0041 , H04L1/0043 , H04L1/0061 , H04L1/0063 , H04L1/0065
Abstract: Embodiment techniques map parity bits to sub-channels based on their row weights. The row weight for a sub-channel may be viewed as the number of “ones” in the corresponding row of the Kronecker matrix or as a power of 2 with the exponent (i.e. the hamming weight) being the number of “ones” in the binary representation of the sub-channel index (further described below). In one embodiment, candidate sub-channels that have certain row weight values are reserved for parity bit(s). Thereafter, K information bits may be mapped to the K most reliable remaining sub-channels, and a number of frozen bits (e.g. N−K) may be mapped to the least reliable remaining sub-channels. Parity bits may then mapped to the candidate sub-channels, and parity bit values are determined based on a function of the information bits.
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公开(公告)号：US09846581B2
公开(公告)日：2017-12-19
申请号：US14480556
申请日：2014-09-08
Applicant: Huawei Technologies Co., Ltd.
Inventor： Tao Huang , Yiqun Ge , Qifan Zhang , Wuxian Shi , Wen Tong
CPC classification number: G06F9/30145 , G06F1/08 , G06F1/10 , G06F9/30036 , G06F9/30189 , G06F9/3826 , G06F9/3828 , G06F9/3836 , G06F9/3851 , G06F9/3853 , G06F9/3871 , G06F9/3877 , G06F9/3885 , G06F9/3889 , G06F9/3891 , G06F9/5011 , G06F15/8007 , G06F15/8053 , G06F15/8092 , G06F2009/3883
Abstract: A clock-less asynchronous processor comprising a plurality of parallel asynchronous processing logic circuits, each processing logic circuit configured to generate an instruction execution result. The processor comprises an asynchronous instruction dispatch unit coupled to each processing logic circuit, the instruction dispatch unit configured to receive multiple instructions from memory and dispatch individual instructions to each of the processing logic circuits. The processor comprises a crossbar coupled to an output of each processing logic circuit and to the dispatch unit, the crossbar configured to store the instruction execution results.
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公开(公告)号：US09720880B2
公开(公告)日：2017-08-01
申请号：US14480562
申请日：2014-09-08
Applicant: Huawei Technologies Co., Ltd.
Inventor： Yiqun Ge , Wuxian Shi , Qifan Zhang , Tao Huang , Wen Tong
CPC classification number: G06F15/825 , G06F9/30058 , G06F9/38 , G06F9/3842 , G06F9/3861 , G06F9/3869 , G06F9/3871
Abstract: Embodiments are provided for an asynchronous processor using master and assisted tokens. In an embodiment, an apparatus for an asynchronous processor comprises a memory to cache a plurality of instructions, a feedback engine to decode the instructions from the memory, and a plurality of XUs coupled to the feedback engine and arranged in a token ring architecture. Each one of the XUs is configured to receive an instruction of the instructions form the feedback engine, and receive a master token associated with a resource and further receive an assisted token for the master token. Upon determining that the assisted token and the master token are received in an abnormal order, the XU is configured to detect an operation status for the instruction in association with the assisted token, and upon determining a needed action in accordance with the operation status and the assisted token, perform the needed action.
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公开(公告)号：US09535698B2
公开(公告)日：2017-01-03
申请号：US14480522
申请日：2014-09-08
Applicant: Huawei Technologies Co., Ltd.
Inventor： Tao Huang , Qifan Zhang , Wuxian Shi , Yiqun Ge , Wen Tong
Abstract: A clock-less asynchronous processing circuit or system having a plurality of pipelined processing stages utilizes self-clocked generators to tune the delay needed in each of the processing stages to complete the processing cycle. Because different processing stages may require different amounts of time to complete processing or may require different delays depending on the processing required in a particular stage, the self-clocked generators may be tuned to each stage's necessary delay(s) or may be programmably configured.
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