公开(公告)号：US20060241802A1

公开(公告)日：2006-10-26

申请号：US11228361

申请日：2005-09-19

Applicant: Chien-Chung Chen ,  Sheng-Jen Wang ,  Yu-Wen Ho

Inventor： Chien-Chung Chen ,  Sheng-Jen Wang ,  Yu-Wen Ho

IPC: G06F19/00

CPC classification number: H01L21/67276 ,  G05B15/02 ,  G05B23/024 ,  G05B2219/1112 ,  G05B2219/45031 ,  G05B2223/02

Abstract: A real-time management method for manufacturing management and yield rate analysis integration. A plurality of yield rates relating to wafer products are summed and averaged for a historical yield rate. Multiple representational inline QC parameters are selected. A statistical process is implemented and, if no extreme value and collinear parameter exists and if analysis results satisfy normal distribution, multiple optimum inline QC parameters are selected from the representational inline QC parameters. Weights of each optimum inline QC parameter are calculated. A predicted yield rate is calculated according to the historical yield rate, weights, and a plurality of measurement and target values relating to the wafer products.

Abstract translation: 制造管理和产出率分析整合的实时管理方法。 将与晶片产品相关的多个屈服率以历史产量率相加和平均。 选择多个代表性的在线QC参数。 实施统计过程，如果没有极值和共线参数存在，并且如果分析结果满足正态分布，则从表示的在线QC参数中选择多个最佳在线QC参数。 计算每个最佳在线QC参数的权值。 根据历史收益率，权重以及与晶片产品相关的多个测量值和目标值来计算预测收益率。

公开(公告)号：US06807454B2

公开(公告)日：2004-10-19

申请号：US10249103

申请日：2003-03-17

Applicant: Sheng-Jen Wang ,  Long-Hui Lin

Inventor： Sheng-Jen Wang ,  Long-Hui Lin

IPC: G06F1900

CPC classification number: H01L21/67288 ,  G05B19/41875 ,  G05B2219/32189 ,  G05B2219/32207 ,  G05B2219/32222 ,  Y02P90/14 ,  Y02P90/22

Abstract: A method for automatically controlling defect-specification in a semiconductor manufacturing process is provided. The method provides a module to detect a position, number, size, and intensity signals of defects on a processed patterned wafer. The module further compares the patterned wafer with a normal wafer to preliminarily classify the patterned wafer and creates a defect map. Then, a defect management system is provided to execute a spatial pattern recognition procedure to determine whether or not the corresponding special pattern can be recognized. Finally, messages will be automatically sent by the defect management system to inform related e-mail accounts according to results of the recognition of the special pattern.

Abstract translation: 提供了一种在半导体制造过程中自动控制缺陷规格的方法。 该方法提供了一种模块，用于检测经处理的图案化晶片上的缺陷的位置，数量，尺寸和强度信号。 该模块进一步将图案化晶片与正常晶片进行比较，以对图案化晶片进行初步分类并创建缺陷图。 然后，提供缺陷管理系统来执行空间模式识别过程，以确定是否可以识别对应的特殊模式。 最后，消息将由缺陷管理系统自动发送，以根据特殊模式的识别结果通知相关的电子邮件帐户。

公开(公告)号：US09497466B2

公开(公告)日：2016-11-15

申请号：US13304372

申请日：2011-11-24

Applicant: Chia-Yun Cheng ,  Sheng-Jen Wang ,  Yun-Feng Tseng ,  Jun Cui

Inventor： Chia-Yun Cheng ,  Sheng-Jen Wang ,  Yun-Feng Tseng ,  Jun Cui

IPC: G06F3/00 ,  H04N19/129 ,  H04N19/176 ,  H04N19/174 ,  H04N19/44 ,  H04N19/423 ,  H04N19/436 ,  G06F13/38 ,  H04L12/861 ,  G06F5/10

CPC classification number: H04N19/129 ,  G06F5/10 ,  G06F13/385 ,  H04L49/90 ,  H04N19/174 ,  H04N19/176 ,  H04N19/423 ,  H04N19/436 ,  H04N19/44

Abstract: An exemplary buffering apparatus for buffering a multi-partition video/image bitstream which transmits a plurality of compressed frames each having a plurality of partitions includes a first bitstream buffer and a second bitstream buffer. The first bitstream buffer is arranged to buffer data of a first partition of the partitions of a specific compressed frame. The second bitstream buffer is arranged to buffer data of a second partition of the partitions of the specific compressed frame.

Abstract translation: 用于缓冲发送多个具有多个分区的多个压缩帧的多分区视频/图像比特流的示例性缓冲装置包括第一比特流缓冲器和第二比特流缓冲器。 第一比特流缓冲器被布置为缓冲特定压缩帧的分区的第一分区的数据。 第二比特流缓冲器被布置为缓冲特定压缩帧的分区的第二分区的数据。

公开(公告)号：US07260444B2

公开(公告)日：2007-08-21

申请号：US11228361

申请日：2005-09-19

Applicant: Chien-Chung Chen ,  Sheng-Jen Wang ,  Yu-Wen Ho

Inventor： Chien-Chung Chen ,  Sheng-Jen Wang ,  Yu-Wen Ho

IPC: G06F19/00

CPC classification number: H01L21/67276 ,  G05B15/02 ,  G05B23/024 ,  G05B2219/1112 ,  G05B2219/45031 ,  G05B2223/02

Abstract: A real-time management method for manufacturing management and yield rate analysis integration. A plurality of yield rates relating to wafer products are summed and averaged for a historical yield rate. Multiple representational inline QC parameters are selected. A statistical process is implemented and, if no extreme value and collinear parameter exists and if analysis results satisfy normal distribution, multiple optimum inline QC parameters are selected from the representational inline QC parameters. Weights of each optimum inline QC parameter are calculated. A predicted yield rate is calculated according to the historical yield rate, weights, and a plurality of measurement and target values relating to the wafer products.

Abstract translation: 制造管理和产出率分析整合的实时管理方法。 将与晶片产品相关的多个屈服率以历史产量率相加和平均。 选择多个代表性的在线QC参数。 实施统计过程，如果没有极值和共线参数存在，并且如果分析结果满足正态分布，则从表示的在线QC参数中选择多个最佳在线QC参数。 计算每个最佳在线QC参数的权值。 根据历史收益率，权重以及与晶片产品相关的多个测量值和目标值来计算预测收益率。

公开(公告)号：US06531776B2

公开(公告)日：2003-03-11

申请号：US09940852

申请日：2001-08-29

Applicant: Ben Min-Jer Lin ,  Sheng-Jen Wang

Inventor： Ben Min-Jer Lin ,  Sheng-Jen Wang

IPC: H01L2940

CPC classification number: H01L21/7682 ,  H01L21/76885 ,  H01L23/5222 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a semiconductor device having reduced interconnect-line parasitic capacitance is provided. The method includes the following steps. First, a substrate is provided and a plurality of interconnect lines are formed on the substrate. A barrier layer is then formed. Next, the barrier layer is hardened and thinned so as to make the barrier layer having a thin-film attribute. Following that, a separation layer is formed by filling the space between and above the interconnect lines with a dielectric. Then, the dielectric is foamed. After that, an insulating layer is formed. Finally, the dielectric is condensed such that air gaps are formed in the separation layer.