公开(公告)号：US20230093823A1

公开(公告)日：2023-03-30

申请号：US17041340

申请日：2019-12-18

Applicant: Intel Corporation

Inventor： Anbang Yao ,  Ping Hu ,  Yangyuxuan Kang ,  Yurong Chen

IPC: G06N3/04 ,  G06N3/08

Abstract: Methods, apparatus, systems, and articles of manufacture for modifying a machine learning model are disclosed. An example apparatus includes a supervised branch inserter to insert a supervised branch into a machine learning model at an identified location, a first cluster generator to generate a first cluster of the inserted supervised branch using a first clustering technique, a second cluster generator to generate a second cluster of the inserted supervised branch using a second clustering technique, the second clustering technique different from the first clustering technique, a cluster joiner to join the first cluster and the second cluster to form a clustering block, the clustering block appended to an end of the supervised branch, and a propagation strategy executor to execute a propagation training strategy to modify a parameter of the machine learning model.

公开(公告)号：US20230061670A1

公开(公告)日：2023-03-02

申请号：US17978573

申请日：2022-11-01

Applicant: Intel Corporation

Inventor： Elmoustapha Ould-Ahmed-Vall ,  Sara S. Baghsorkhi ,  Anbang Yao ,  Kevin Nealis ,  Xiaoming Chen ,  Altug Koker ,  Abhishek R. Appu ,  John C. Weast ,  Mike B. Macpherson ,  Dukhwan Kim ,  Linda L. Hurd ,  Ben J. Ashbaugh ,  Barath Lakshmanan ,  Liwei Ma ,  Joydeep Ray ,  Ping T. Tang ,  Michael S. Strickland

IPC: G06T1/20 ,  G06N3/08 ,  G06F9/38 ,  G06N3/063 ,  G06F9/30 ,  G06N20/00 ,  G06N3/04 ,  G06F9/50 ,  G06F7/483

Abstract: One embodiment provides an apparatus comprising a memory stack including multiple memory dies and a parallel processor including a plurality of multiprocessors. Each multiprocessor has a single instruction, multiple thread (SIMT) architecture, the parallel processor coupled to the memory stack via one or more memory interfaces. At least one multiprocessor comprises a multiply-accumulate circuit to perform multiply-accumulate operations on matrix data in a stage of a neural network implementation to produce a result matrix comprising a plurality of matrix data elements at a first precision, precision tracking logic to evaluate metrics associated with the matrix data elements and indicate if an optimization is to be performed for representing data at a second stage of the neural network implementation, and a numerical transform unit to dynamically perform a numerical transform operation on the matrix data elements based on the indication to produce transformed matrix data elements at a second precision.

公开(公告)号：US20230039729A1

公开(公告)日：2023-02-09

申请号：US17963539

申请日：2022-10-11

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Altug Koker ,  Linda L. Hurd ,  Dukhwan Kim ,  Mike B. MacPherson ,  John C. Weast ,  Justin E. Gottschlich ,  Jingyi Jin ,  Barath Lakshmanan ,  Chandrasekaran Sakthivel ,  Michael S. Strickland ,  Joydeep Ray ,  Kamal Sinha ,  Prasoonkumar Surti ,  Balaji Vembu ,  Ping T. Tang ,  Anbang Yao ,  Tatiana Shpeisman ,  Xiaoming Chen

IPC: G05B13/02 ,  G05D1/00 ,  G06N3/04 ,  G06N3/02 ,  G06N5/04 ,  G06N20/00

Abstract: Methods and apparatus relating to autonomous vehicle neural network optimization techniques are described. In an embodiment, the difference between a first training dataset to be used for a neural network and a second training dataset to be used for the neural network is detected. The second training dataset is authenticated in response to the detection of the difference. The neural network is used to assist in an autonomous vehicle/driving. Other embodiments are also disclosed and claimed.

公开(公告)号：US11461107B2

公开(公告)日：2022-10-04

申请号：US16227645

申请日：2018-12-20

Applicant: Intel Corporation

Inventor： Elmoustapha Ould-Ahmed-Vall ,  Barath Lakshmanan ,  Tatiana Shpeisman ,  Joydeep Ray ,  Ping T. Tang ,  Michael Strickland ,  Xiaoming Chen ,  Anbang Yao ,  Ben J. Ashbaugh ,  Linda L. Hurd ,  Liwei Ma

IPC: G06F9/38 ,  G06F9/30 ,  G06F15/80 ,  G06F13/42 ,  G06F13/40 ,  G06N20/00 ,  G06T1/20 ,  G06N3/04 ,  G06N3/063 ,  G06N3/08 ,  G06N20/10 ,  G06F9/50 ,  G06N3/00

Abstract: One embodiment provides for a general-purpose graphics processing unit comprising a streaming multiprocessor having a single instruction, multiple thread (SIMT) architecture including hardware multithreading. The streaming multiprocessor comprises multiple processing blocks including multiple processing cores. The processing cores include independent integer and floating-point data paths that are configurable to concurrently execute multiple independent instructions. A memory is coupled with the multiple processing blocks.

公开(公告)号：US11409537B2

公开(公告)日：2022-08-09

申请号：US15819167

申请日：2017-11-21

Applicant: Intel Corporation

Inventor： Elmoustapha Ould-Ahmed-Vall ,  Barath Lakshmanan ,  Tatiana Shpeisman ,  Joydeep Ray ,  Ping T. Tang ,  Michael Strickland ,  Xiaoming Chen ,  Anbang Yao ,  Ben J. Ashbaugh ,  Linda L. Hurd ,  Liwei Ma

IPC: G06F9/38 ,  G06F9/30 ,  G06F13/40 ,  G06F13/42 ,  G06N20/00 ,  G06T1/20 ,  G06N3/04 ,  G06N3/063 ,  G06N3/08 ,  G06N20/10 ,  G06F9/50 ,  G06F15/80 ,  G06N3/00

Abstract: One embodiment provides for a graphics processing unit (GPU) to accelerate machine learning operations, the GPU comprising an instruction cache to store a first instruction and a second instruction, the first instruction to cause the GPU to perform a floating-point operation, including a multi-dimensional floating-point operation, and the second instruction to cause the GPU to perform an integer operation; and a general-purpose graphics compute unit having a single instruction, multiple thread (SIMT) architecture, the general-purpose graphics compute unit to simultaneously execute the first instruction and the second instruction, wherein the integer operation corresponds to a memory address calculation.

公开(公告)号：US11157764B2

公开(公告)日：2021-10-26

申请号：US16489084

申请日：2017-03-27

Applicant: INTEL CORPORATION

Inventor： Libin Wang ,  Anbang Yao ,  Jianguo Li ,  Yurong Chen

IPC: G06K9/62 ,  G06K9/46 ,  G06N3/04

Abstract: An example apparatus for semantic image segmentation includes a receiver to receive an image to be segmented. The apparatus also includes a gated dense pyramid network comprising a plurality of gated dense pyramid (GDP) blocks to be trained to generate semantic labels for each pixel in the received image. The apparatus further includes a generator to generate a segmented image based on the generated semantic labels.

公开(公告)号：US11157727B2

公开(公告)日：2021-10-26

申请号：US16647722

申请日：2017-12-27

Applicant: INTEL CORPORATION

Inventor： Ping Hu ,  Anbang Yao ,  Jia Wei ,  Dongqi Cai ,  Yurong Chen

IPC: G06K9/62 ,  G06K9/00 ,  G06K9/66 ,  G06N3/08

Abstract: Techniques are provided for neural network based, human attribute recognition, guided by anatomical key-points and statistic correlation models. Attributes include characteristics that can be visibly identified or inferred from an image, such as gender, hairstyle, clothing style, etc. A methodology implementing the techniques according to an embodiment includes applying an attribute feature extraction (AFE) convolutional neural network (CNN) to an image of a human to generate attribute feature maps based on the image. The method further includes applying a key-point guided proposal (KPG) CNN to the image of the human to generate proposed hierarchical regions of the image based on associated anatomical key-points. The method further includes generating recognition probabilities for the human attributes using a CNN combination layer that incorporates the attribute feature maps, the proposed hierarchical regions, and statistical correlation models (SCMs) which provide correlations between the features of the attribute feature maps and the proposed hierarchical regions.

公开(公告)号：US11080811B2

公开(公告)日：2021-08-03

申请号：US16446398

申请日：2019-06-19

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Altug Koker ,  Linda L. Hurd ,  Dukhwan Kim ,  Mike B. Macpherson ,  John C. Weast ,  Feng Chen ,  Farshad Akhbari ,  Narayan Srinivasa ,  Nadathur Rajagopalan Satish ,  Joydeep Ray ,  Ping T. Tang ,  Michael S. Strickland ,  Xiaoming Chen ,  Anbang Yao ,  Tatiana Shpeisman

IPC: G06T1/20 ,  G06F3/14 ,  G06F9/30 ,  G06F9/38 ,  G06N3/04 ,  G06N3/063 ,  G06N3/08 ,  G06T15/00 ,  G09G5/36 ,  G06T15/04

Abstract: An apparatus to facilitate compute optimization is disclosed. The apparatus includes a mixed precision core to perform a mixed precision multi-dimensional matrix multiply and accumulate operation on 16-bit and/or 32 bit floating-point elements.

公开(公告)号：US20210142448A1

公开(公告)日：2021-05-13

申请号：US17090170

申请日：2020-11-05

Applicant: Intel Corporation

Inventor： Anbang Yao ,  Ming Lu ,  Yikai Wang ,  Xiaoming Chen ,  Junjie Huang ,  Tao Lv ,  Yuanke Luo ,  Yi Yang ,  Feng Chen ,  Zhiming Wang ,  Zhiqiao Zheng ,  Shandong Wang

IPC: G06T5/00 ,  G06N3/04

Abstract: Embodiments are generally directed to an adaptive deformable kernel prediction network for image de-noising. An embodiment of a method for de-noising an image by a convolutional neural network implemented on a compute engine, the image including a plurality of pixels, the method comprising: for each of the plurality of pixels of the image, generating a convolutional kernel having a plurality of kernel values for the pixel; generating a plurality of offsets for the pixel respectively corresponding to the plurality of kernel values, each of the plurality of offsets to indicate a deviation from a pixel position of the pixel; determining a plurality of deviated pixel positions based on the pixel position of the pixel and the plurality of offsets; and filtering the pixel with the convolutional kernel and pixel values of the plurality of deviated pixel positions to obtain a de-noised pixel.

公开(公告)号：US20210124579A1

公开(公告)日：2021-04-29

申请号：US17115989

申请日：2020-12-09

Applicant: Intel Corporation

Inventor： Himanshu Kaul ,  Mark A. Anders ,  Sanu K. Mathew ,  Anbang Yao ,  Joydeep Ray ,  Ping T. Tang ,  Michael S. Strickland ,  Xiaoming Chen ,  Tatiana Shpeisman ,  Abhishek R. Appu ,  Altug Koker ,  Kamal Sinha ,  Balaji Vembu ,  Nicolas C. Galoppo Von Borries ,  Eriko Nurvitadhi ,  Rajkishore Barik ,  Tsung-Han Lin ,  Vasanth Ranganathan ,  Sanjeev Jahagirdar

IPC: G06F9/30 ,  G09G5/393 ,  G06F9/38 ,  G06F7/483 ,  G06F7/544 ,  G06N3/04 ,  G06N3/063 ,  G06N3/08

Abstract: One embodiment provides for a graphics processing unit to accelerate machine-learning operations, the graphics processing unit comprising a multiprocessor having a single instruction, multiple thread (SIMT) architecture, the multiprocessor to execute at least one single instruction; and a first compute unit included within the multiprocessor, the at least one single instruction to cause the first compute unit to perform a two-dimensional matrix multiply and accumulate operation, wherein to perform the two-dimensional matrix multiply and accumulate operation includes to compute a 32-bit intermediate product of 16-bit operands and to compute a 32-bit sum based on the 32-bit intermediate product.