公开(公告)号：US20180307533A1

公开(公告)日：2018-10-25

申请号：US15493698

申请日：2017-04-21

Applicant: Intel Corporation

Inventor： Kun Tian ,  David J. Cowperthwaite ,  Murali Ramadoss ,  Balaji Vembu ,  Zhi Wang ,  Eric C. Samson ,  Altug Koker ,  Abhishek R. Appu ,  Joydeep Ray

IPC: G06F9/48 ,  G06T1/20

CPC classification number: G06F9/4887 ,  G06F9/4831 ,  G06T1/20 ,  G06T1/60 ,  G06T2210/52

Abstract: A mechanism is described for facilitating multi-level scheduling of workloads in computing devices. A method of embodiments, as described herein, includes facilitating multiple levels of scheduling for processing of workloads using multiple levels of queues, where the workloads are associated with a device including a processor of a computing device.

公开(公告)号：US11551400B2

公开(公告)日：2023-01-10

申请号：US17072253

申请日：2020-10-16

Applicant: INTEL CORPORATION

Inventor： Prasoonkumar Surti ,  Tomas G. Akenine-Moller ,  David J. Cowperthwaite ,  Kun Tian ,  Peter L. Doyle ,  Brent E. Insko ,  Adam T. Lake

IPC: G06T15/00 ,  G06T1/20 ,  G06T1/60 ,  G06T15/40 ,  G06T15/50

Abstract: A virtual reality apparatus and method are described for tile-based rendering. For example, one embodiment of an apparatus comprises: a set of on-chip geometry buffers including a first buffer to store geometry data, and a set of pointer buffers to store pointers to the geometry data; a tile-based immediate mode rendering (TBIMR) module to perform tile-based immediate mode rendering using geometry data and pointers stored within the set of on-chip geometry buffers; spill circuitry to determine when the on-chip geometry buffers are over-subscribed and responsively spill additional geometry data and/or pointers to an off-chip memory; and a prefetcher to start prefetching the geometry data from the off-chip memory as space becomes available within the on-chip geometry buffers, the TBIMR module to perform tile-based immediate mode rendering using the geometry data prefetched from the off-chip memory.

公开(公告)号：US11514550B2

公开(公告)日：2022-11-29

申请号：US16916670

申请日：2020-06-30

Applicant: INTEL CORPORATION

Inventor： Yunbiao Lin ,  Changliang Wang ,  Satyanantha Ramagopal Musunuri ,  David Puffer ,  David J. Cowperthwaite ,  Bryan R. White ,  Balaji Vembu

IPC: G06T1/20 ,  G06T1/60 ,  G06F3/14 ,  G06F9/451 ,  G09G5/00 ,  G09G5/36 ,  G06F12/10 ,  G06F12/1009

Abstract: An apparatus and method for managing pipes and planes within a virtual graphics processing engine. For example, one embodiment of a graphics processing apparatus comprises: a graphics processor comprising one or more display pipes to render one or more display planes, each of the one or more display pipes comprising a set of graphics processing hardware resources for executing graphics commands and rendering graphics images in the one or more display planes; and pipe and plane management hardware logic to manage pipe and plane assignment, the pipe and plane management hardware logic to associate a first virtual machine (VM) with one or more virtual display planes and to maintain a mapping between the one or more virtual display planes and at least one physical display plane.

公开(公告)号：US11449396B2

公开(公告)日：2022-09-20

申请号：US16573364

申请日：2019-09-17

Applicant: Intel Corporation

Inventor： Christopher Cormack ,  David J. Cowperthwaite ,  Matthew Curfman

IPC: G06F11/14 ,  G06F9/455 ,  G06F13/42 ,  B60W50/04 ,  B60W50/00

Abstract: In various embodiments, an apparatus includes a system-on-chip (SoC) to be disposed in a vehicle having a plurality of cores; a hypervisor arranged to partition the cores into at least two domains, an operational domain and a failover domain; a first operating system (OS) arranged to manage execution of at least a first application in the operational domain to provide a first plurality of functions for the vehicle; a second OS arranged to manage execution of at least a second application in the failover domain to provide a second plurality of functions for the vehicle, on occurrence of a failure of the first application. The second functions comprise a subset of the first functions or less embellished versions of some of the first functions, and the second OS has less capabilities than the first OS. Other embodiments, including storage media and methods, are also described and claimed.

公开(公告)号：US20220245752A1

公开(公告)日：2022-08-04

申请号：US17685445

申请日：2022-03-03

Applicant: Intel Corporation

Inventor： Murali Ramadoss ,  Balaji Vembu ,  Eric C. Samson ,  Kun Tian ,  David J. Cowperthwaite ,  Altug Koker ,  Zhi Wang ,  Joydeep Ray ,  Subramaniam M. Maiyuran ,  Abhishek R. Appu

IPC: G06T1/20 ,  G06F9/48 ,  G06F9/50 ,  G06F9/38

Abstract: Embodiments described herein provide techniques enable a graphics processor to continue processing operations during the reset of a compute unit that has experienced a hardware fault. Threads and associated context state for a faulted compute unit can be migrated to another compute unit of the graphics processor and the faulting compute unit can be reset while processing operations continue.

公开(公告)号：US10380039B2

公开(公告)日：2019-08-13

申请号：US15482690

申请日：2017-04-07

Applicant: Intel Corporation

Inventor： Niranjan L. Cooray ,  Satyeshwar Singh ,  Sameer KP ,  Ankur N. Shah ,  Kun Tian ,  Abhishek R. Appu ,  Altug Koker ,  Joydeep Ray ,  Balaji Vembu ,  Pattabhiraman K ,  David Puffer ,  David J. Cowperthwaite ,  Rajesh M. Sankaran

IPC: G06F12/109 ,  G06F11/07 ,  G06F13/16 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/1036 ,  G06F12/0802 ,  G06F13/40

Abstract: An apparatus and method are described for implementing memory management in a graphics processing system. For example, one embodiment of an apparatus comprises: a first plurality of graphics processing resources to execute graphics commands and process graphics data; a first memory management unit (MMU) to communicatively couple the first plurality of graphics processing resources to a system-level MMU to access a system memory; a second plurality of graphics processing resources to execute graphics commands and process graphics data; a second MMU to communicatively couple the second plurality of graphics processing resources to the first MMU; wherein the first MMU is configured as a master MMU having a direct connection to the system-level MMU and the second MMU comprises a slave MMU configured to send memory transactions to the first MMU, the first MMU either servicing a memory transaction or sending the memory transaction to the system-level MMU on behalf of the second MMU.

公开(公告)号：US10191759B2

公开(公告)日：2019-01-29

申请号：US15025735

申请日：2013-11-27

Applicant: INTEL CORPORATION

Inventor： David J. Cowperthwaite ,  Murali Ramadoss ,  Ankur N. Shah ,  Balaji Vembu ,  Altug Koker ,  Aditya Navale

IPC: G06F9/455 ,  G06F9/50 ,  G06T1/20

Abstract: In an embodiment, a system includes a graphics processing unit (GPU) that includes one or more GPU engines, and a microcontroller. The microcontroller is to assign a respective schedule slot for each of a plurality of virtual machines (VMs). When a particular VM is scheduled to access a first GPU engine, the particular VM has exclusive access to the first GPU engine. Other embodiments are described and claimed.

公开(公告)号：US20180308198A1

公开(公告)日：2018-10-25

申请号：US15493522

申请日：2017-04-21

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Balaji Vembu ,  Altug Koker ,  Bryan R. White ,  David J. Cowperthwaite ,  Joydeep Ray ,  Murali Ramadoss

IPC: G06T1/20 ,  G06F9/50 ,  G06F9/455

Abstract: An apparatus to facilitate partitioning of a graphics device is disclosed. The apparatus includes a plurality of engines and logic to partition the plurality of engines to facilitate independent access to each engine within the plurality of engines.

公开(公告)号：US11360914B2

公开(公告)日：2022-06-14

申请号：US17008991

申请日：2020-09-01

Applicant: Intel Corporation

Inventor： Niranjan L. Cooray ,  Abhishek R. Appu ,  Altug Koker ,  Joydeep Ray ,  Balaji Vembu ,  Pattabhiraman K ,  David Puffer ,  David J. Cowperthwaite ,  Rajesh M. Sankaran ,  Satyeshwar Singh ,  Sameer Kp ,  Ankur N. Shah ,  Kun Tian

IPC: G06F12/109 ,  G06F11/07 ,  G06F13/16 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/1036 ,  G06F12/0802 ,  G06F13/40

Abstract: An apparatus and method are described for implementing memory management in a graphics processing system. For example, one embodiment of an apparatus comprises: a first plurality of graphics processing resources to execute graphics commands and process graphics data; a first memory management unit (MMU) to communicatively couple the first plurality of graphics processing resources to a system-level MMU to access a system memory; a second plurality of graphics processing resources to execute graphics commands and process graphics data; a second MMU to communicatively couple the second plurality of graphics processing resources to the first MMU; wherein the first MMU is configured as a master MMU having a direct connection to the system-level MMU and the second MMU comprises a slave MMU configured to send memory transactions to the first MMU, the first MMU either servicing a memory transaction or sending the memory transaction to the system-level MMU on behalf of the second MMU.

公开(公告)号：US11341600B2

公开(公告)日：2022-05-24

申请号：US16681983

申请日：2019-11-13

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Balaji Vembu ,  Altug Koker ,  Bryan R. White ,  David J. Cowperthwaite ,  Joydeep Ray ,  Murali Ramadoss

IPC: G06F15/80 ,  G06T1/20 ,  G06F9/50 ,  G06F9/455

Abstract: An apparatus to facilitate partitioning of a graphics device is disclosed. The apparatus includes a plurality of engines and logic to partition the plurality of engines to facilitate independent access to each engine within the plurality of engines.