公开(公告)号：US11200176B2

公开(公告)日：2021-12-14

申请号：US17009245

申请日：2020-09-01

Applicant: Intel Corporation

Inventor： Raj K. Ramanujan ,  Glenn J Hinton ,  David J. Zimmerman

IPC: G06F12/00 ,  G06F12/0891 ,  G06F12/0895 ,  G06F1/3234 ,  G06F1/3225 ,  G06F12/0868 ,  G06F12/0873 ,  G06F12/0804 ,  G06F11/07 ,  G06F1/30 ,  G06F12/0864

Abstract: A system and method are described for flushing a specified region of a memory side cache (MSC) within a multi-level memory hierarchy. For example, a computer system according to one embodiment comprises: a memory subsystem comprised of a non-volatile system memory and a volatile memory side cache (MSC) for caching portions of the non-volatile system memory; and a flush engine for flushing a specified region of the MSC to the non-volatile system memory in response to a deactivation condition associated with the specified region of the MSC.

公开(公告)号：US10026475B2

公开(公告)日：2018-07-17

申请号：US14879008

申请日：2015-10-08

Applicant: Intel Corporation

Inventor： Shekoufeh Qawami ,  Rajesh Sundaram ,  David J. Zimmerman ,  Blaise Fanning

IPC: G06F3/00 ,  G11C13/00 ,  G06F9/30 ,  G06F12/02 ,  G06F1/32 ,  G11C16/06

Abstract: Examples are disclosed for adaptive configuration of non-volatile memory. The examples include a mode register configured to include default and updated values to indicate one or more configurations of the non-volatile memory. The examples may also include discoverable capabilities maintained in a configuration table that may indicate memory address lengths and/or operating power states.

公开(公告)号：US20170169900A1

公开(公告)日：2017-06-15

申请号：US15293123

申请日：2016-10-13

Applicant: Intel Corporation

Inventor： David J. Zimmerman

IPC: G11C29/32 ,  G01R31/3185 ,  G11C11/408 ,  G01R31/3177

CPC classification number: G11C29/32 ,  G01R31/3177 ,  G01R31/318513 ,  G01R31/318558 ,  G01R31/318572 ,  G11C5/04 ,  G11C11/4087 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A boundary scan chain for stacked memory. An embodiment of a memory device includes a system element and a memory stack including one or more memory die layers, each memory die layer including input-output (I/O) cells and a boundary scan chain for the I/O cells. A boundary scan chain of a memory die layer includes a scan chain portion for each of the I/O cells, the scan chain portion for an I/O cell including a first scan logic multiplexer a scan logic latch, an input of the scan logic latch being coupled with an output of the first scan logic multiplexer, and a decoder to provide command signals to the boundary scan chain.

公开(公告)号：US09036718B2

公开(公告)日：2015-05-19

申请号：US14132703

申请日：2013-12-18

Applicant: Intel Corporation

Inventor： David J. Zimmerman ,  Michael W. Williams

IPC: H04B3/00 ,  H04L25/00 ,  G06F13/28 ,  G11C5/06 ,  G11C7/10 ,  G11C11/4076 ,  G11C11/4096

CPC classification number: G06F13/28 ,  G11C5/066 ,  G11C7/10 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/109 ,  G11C11/4076 ,  G11C11/4096

Abstract: Embodiments provide access to a memory over a high speed serial link at slower speeds than the high speed serial links regular operation. An embodiment may comprise a memory apparatus with a differential receiver coupled to a protocol recognition circuit, a low speed receiving circuit that has a first receiver coupled with a first input of the differential receiver and a second receiver coupled with a second input of the differential receiver, wherein the low speed receiving circuit is coupled with the protocol recognition circuit, allowing the first and second receivers to access the protocol recognition block at a different frequency than the differential receiver.