公开(公告)号：US20190332278A1

公开(公告)日：2019-10-31

申请号：US16428802

申请日：2019-05-31

Applicant: Intel Corporation

Inventor： Rajesh Sundaram ,  Albert Fazio ,  Derchang Kau ,  Shekoufeh Qawami

IPC: G06F3/06 ,  G11C13/00 ,  G06F13/16 ,  G06F12/02

Abstract: Cross point memory architectures, devices, systems, and methods are disclosed and described, and can include a cross point memory core subsystem having increased bandwidth that is scalable. The memory core can include a plurality of independently operating partitions, each comprising a plurality of cross point memory arrays.

公开(公告)号：US09613698B2

公开(公告)日：2017-04-04

申请号：US15154465

申请日：2016-05-13

Applicant: INTEL CORPORATION

Inventor： Davide Mantegazza ,  Kiran Pangal ,  Gerard H. Joyce ,  Prashant Damle ,  Derchang Kau ,  Davide Fugazza

IPC: G11C13/00

CPC classification number: G11C13/0097 ,  G11C13/0004 ,  G11C13/0038 ,  G11C13/0069 ,  G11C2013/0092

Abstract: Embodiments of the present disclosure describe techniques and configurations for word-line path isolation in a phase change memory (PCM) device. In an embodiment, a method includes increasing a current through a memory cell of a phase change memory (PCM) device, wherein the memory cell is coupled with a capacitor and subsequent to said increasing the current, generating a transient current through the memory cell by discharge of the capacitor to reset the memory cell. In another embodiment, a method includes increasing a current through a memory cell of a phase change memory (PCM) device and controlling the current to be greater than a threshold current and lower than a hold current of the memory cell to set the memory cell. Other embodiments may be described and/or claimed.

公开(公告)号：US12268011B2

公开(公告)日：2025-04-01

申请号：US17118385

申请日：2020-12-10

Applicant: Intel Corporation

Inventor： Prashant Majhi ,  Derchang Kau ,  Max Hineman

IPC: H01L27/00 ,  G11C5/06 ,  G11C13/00 ,  H01L27/06 ,  H10B63/00 ,  H10N70/00 ,  H10N70/20

Abstract: A memory device structure includes a vertical transistor having a channel between a source and a drain, a gate electrode adjacent the channel, where the gate electrode is in a first direction orthogonal to a longitudinal axis of the channel. A gate dielectric layer is between the gate electrode and the channel A first terminal of a first interconnect is coupled with the source or the drain, where the first interconnect is colinear with the longitudinal axis. The memory device structure further includes a pair of memory cells, where individual ones of the memory cells includes a selector and a memory element, where a first terminal of the individual ones of the memory cell is coupled to a respective second and a third terminal of the first interconnect. A second terminal of the individual ones of the memory cell is coupled to individual ones of the pair of second interconnects.

公开(公告)号：US20220415892A1

公开(公告)日：2022-12-29

申请号：US17358073

申请日：2021-06-25

Applicant: INTEL CORPORATION

Inventor： Wilfred Gomes ,  Abhishek A. Sharma ,  Conor P. Puls ,  Mauro J. Kobrinsky ,  Kevin J. Fischer ,  Derchang Kau ,  Albert Fazio ,  Tahir Ghani

IPC: H01L27/105

Abstract: Integrated circuit (IC) devices with stacked two-level backend memory, and associated systems and methods, are disclosed. An example IC device includes a front end of line (FEOL) layer, including frontend transistors, and a back end of line (BEOL) layer above the FEOL layer. The BEOL layer includes a first memory layer with memory cells of a first type, and a second memory layer with memory cells of a second type. The first memory layer may be between the FEOL layer and the second memory layer, thus forming stacked backend memory. Stacked backend memory architecture may allow significantly increasing density of memory cells in a memory array having a given footprint area, or, conversely, reducing the footprint area of the memory array with a given memory cell density. Implementing two different types of backend memory may advantageously increase functionality and performance of backend memory.

公开(公告)号：US20220190035A1

公开(公告)日：2022-06-16

申请号：US17118377

申请日：2020-12-10

Applicant: Intel Corporation

Inventor： Prashant Majhi ,  Derchang Kau ,  Max Hineman

IPC: H01L27/24 ,  H01L29/24 ,  H01L29/786 ,  H01L21/02 ,  H01L29/66

Abstract: A memory device structure includes a first plurality of line structures, where each line structure, in the first plurality of line structures, includes a first transistor channel. The memory device structure further includes a second plurality of line structures substantially orthogonal to the first plurality of line structures, where each line structure, in the second plurality of line structures, includes a second transistor channel A memory cell is at each cross-point between the first plurality of line structures and the second plurality of line structures.

公开(公告)号：US20160254052A1

公开(公告)日：2016-09-01

申请号：US15154465

申请日：2016-05-13

Applicant: INTEL CORPORATION

Inventor： Davide Mantegazza ,  Kiran Pangal ,  Gerard H. Joyce ,  Prashant Damle ,  Derchang Kau ,  Davide Fugazza

IPC: G11C13/00

CPC classification number: G11C13/0097 ,  G11C13/0004 ,  G11C13/0038 ,  G11C13/0069 ,  G11C2013/0092

Abstract: Embodiments of the present disclosure describe techniques and configurations for word-line path isolation in a phase change memory (PCM) device. In an embodiment, a method includes increasing a current through a memory cell of a phase change memory (PCM) device, wherein the memory cell is coupled with a capacitor and subsequent to said increasing the current, generating a transient current through the memory cell by discharge of the capacitor to reset the memory cell. In another embodiment, a method includes increasing a current through a memory cell of a phase change memory (PCM) device and controlling the current to be greater than a threshold current and lower than a hold current of the memory cell to set the memory cell. Other embodiments may be described and/or claimed.

公开(公告)号：US09368205B2

公开(公告)日：2016-06-14

申请号：US14010417

申请日：2013-08-26

Applicant: INTEL CORPORATION

Inventor： Davide Mantegazza ,  Kiran Pangal ,  Gerard H. Joyce ,  Prashant Damle ,  Derchang Kau ,  Davide Fugazza

IPC: G11C13/00

CPC classification number: G11C13/0097 ,  G11C13/0004 ,  G11C13/0038 ,  G11C13/0069 ,  G11C2013/0092

Abstract: Embodiments of the present disclosure describe techniques and configurations for word-line path isolation in a phase change memory (PCM) device. In an embodiment, a method includes increasing a current through a memory cell of a phase change memory (PCM) device, wherein the memory cell is coupled with a capacitor and subsequent to said increasing the current, generating a transient current through the memory cell by discharge of the capacitor to reset the memory cell. In another embodiment, a method includes increasing a current through a memory cell of a phase change memory (PCM) device and controlling the current to be greater than a threshold current and lower than a hold current of the memory cell to set the memory cell. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例描述了在相变存储器（PCM）设备中的字线路径隔离的技术和配置。 在一个实施例中，一种方法包括增加通过相变存储器（PCM）器件的存储器单元的电流，其中存储器单元与电容器耦合，并且随后增加电流，产生通过存储器单元的瞬态电流，由 放电电容器来重置存储单元。 在另一个实施例中，一种方法包括增加通过相变存储器（PCM）器件的存储器单元的电流，并且控制电流大于阈值电流并且低于存储器单元的保持电流以设置存储器单元。 可以描述和/或要求保护其他实施例。