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    ENCODING ADDITIONAL STATES IN A THREE-DIMENSIONAL CROSSPOINT MEMORY ARCHITECTURE
    1.
    发明申请
    ENCODING ADDITIONAL STATES IN A THREE-DIMENSIONAL CROSSPOINT MEMORY ARCHITECTURE 有权

    公开(公告)号：US20230064007A1

    公开(公告)日：2023-03-02

    申请号：US17408352

    申请日：2021-08-20

    Applicant: Intel Corporation

    Inventor： Rouhollah Mousavi Iraei ,  Kiran Pangal ,  Saad P. Monasa ,  Mini Goel ,  Raymond Zeng ,  Hemant P. Rao

    IPC: G11C13/00

    Abstract: In one embodiment, a state is encoded into a memory cell comprising a phase change material (PM) region and a select device (SD) region by: applying a first current in the memory cell over a first time period, wherein the first current applied over the first time period causes the PM region of the memory cell to be placed into an amorphous state and the SD region of the memory cell to be placed into an amorphous state; and applying a second current in the memory cell over a second time period after the first time period, wherein the second current applied over the third time period causes the SD region of the memory cell to be placed into a crystalline state and the PM region of the memory cell to remain in the amorphous state.

    Multi-level cell (MLC) cross-point memory
    2.
    发明授权
    Multi-level cell (MLC) cross-point memory 有权

    公开(公告)号：US11107523B1

    公开(公告)日：2021-08-31

    申请号：US16828589

    申请日：2020-03-24

    Applicant: Intel Corporation

    Inventor： Sanjay Rangan ,  Kiran Pangal

    IPC: G11C11/00 ,  G11C11/56 ,  G11C13/00

    Abstract: Multi-level cell (MLC) cross-point memory cells can store more than 1 bit per cell. In one example, MLC write operations for cross-point memory can be achieved by independently changing the state of the switch element and the memory element. The memory cell can be programmed to multiple states, such as a high threshold voltage state (where both the memory element and switch element exhibit a high threshold voltage or resistance), a low threshold voltage state (where both the memory element and select element exhibit a low threshold voltage or resistance), and one or more intermediate resistance states. In one example, additional resistance states can be programmed by setting the switch element and memory element to opposite states (e.g., one of the switch element and memory element is in a high resistance state and the other is in a low resistance state) or by placing both the switch element and memory element in different intermediate states.

    Single-bit first error correction
    8.
    发明授权
    Single-bit first error correction 有权

    公开(公告)号：US09698830B2

    公开(公告)日：2017-07-04

    申请号：US13780690

    申请日：2013-02-28

    Applicant: INTEL CORPORATION

    Inventor： Ravi H. Motwani ,  Kiran Pangal

    IPC: H03M13/00 ,  H03M13/37 ,  H03M13/13 ,  H03M13/15

    CPC classification number: H03M13/3715 ,  H03M13/13 ,  H03M13/1515 ,  H03M13/152

    Abstract: Embodiments include device, storage media, and methods for decoding a codeword of encoded data. In embodiments, a processor may be coupled with a decoder and configured to multiply the codeword and a parity-check matrix of the encoded data to produce a syndrome. If the syndrome is non-zero then the processor may identify a bit error in the codeword based at least in part on a comparison of the syndrome to one or more columns of the parity-check matrix. Other embodiments may be described and claimed.

    Techniques to mitigate bias drift for a memory device
    9.
    发明授权
    Techniques to mitigate bias drift for a memory device 有权
    减轻存储器件偏移漂移的技术

    公开(公告)号：US09589634B1

    公开(公告)日：2017-03-07

    申请号：US15087762

    申请日：2016-03-31

    Applicant: Intel Corporation

    Inventor： Rakesh Jeyasingh ,  Nevil N. Gajera ,  Mase J Taub ,  Kiran Pangal

    IPC: G11C13/00 ,  G11C11/56

    CPC classification number: G11C7/12 ,  G11C11/1657 ,  G11C11/1675 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0028 ,  G11C13/0033 ,  G11C13/0069 ,  G11C2213/77

    Abstract: Examples may include techniques to mitigate bias drift for memory cells of a memory device. A first memory cell coupled with a first word-line and a bit-line is selected for a write operation. A second memory cell coupled with a second word-line and the bit-line is de-selected for the write operation. First and second bias voltages are applied to the first word-line and the bit-line during the write operation to program the first memory cell. A third bias voltage is applied to the second word-line during the write operation to reduce or mitigate voltage bias to the second memory cell due to the second bias voltage applied to the bit-line to program the first memory cell.

    Abstract translation: 示例可以包括减轻存储器件的存储器单元的偏移漂移的技术。 选择与第一字线和位线耦合的第一存储器单元用于写入操作。 与第二字线耦合的第二存储单元和位线被取消选择用于写入操作。 第一和第二偏置电压在写入操作期间被施加到第一字线和位线以对第一存储器单元进行编程。 在写入操作期间，第三偏置电压被施加到第二字线，以减少或减轻施加到位线的第二偏置电压来对第二存储器单元的电压偏置，以对第一存储器单元进行编程。

    PROVISION OF HOLDING CURRENT IN NON-VOLATILE RANDOM ACCESS MEMORY
    10.
    发明申请
    PROVISION OF HOLDING CURRENT IN NON-VOLATILE RANDOM ACCESS MEMORY 审中-公开
    在非易失性随机存取存储器中提供保持电流

    公开(公告)号：US20170053698A1

    公开(公告)日：2017-02-23

    申请号：US15347736

    申请日：2016-11-09

    Applicant: Intel Corporation

    Inventor： Dany-Sebastien Ly-Gagnon ,  Kiran Pangal ,  Raymond W. Zeng ,  Mase J. Taub

    IPC: G11C13/00

    CPC classification number: G11C11/00 ,  G06F11/1048 ,  G11C7/04 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0038 ,  G11C13/004 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0045 ,  G11C2013/0078 ,  G11C2013/0092 ,  G11C2213/77 ,  H01L29/06 ,  H04L65/403

    Abstract: Embodiments of the present disclosure describe techniques and configurations for controlling current in a non-volatile random access memory (NVRAM) device. In an embodiment, the NVRAM device may include a plurality of memory cells coupled to a plurality of bit lines forming a bit line node with parasitic capacitance. Each memory cell may comprise a switch device with a required level of a holding current to maintain an on-state of the cell. A voltage supply circuitry and a controller may be coupled with the NVRAM device. The controller may control the circuitry to provide a current pulse that keeps a memory cell in on-state. The pulse may comprise a profile that changes over time from a set point to the holding current level, in response to a discharge of the bit line node capacitance through the memory cell after the set point is achieved. Other embodiments may be described and/or claimed.

    Abstract translation: 本公开的实施例描述了用于控制非易失性随机存取存储器（NVRAM）设备中的电流的技术和配置。 在一个实施例中，NVRAM器件可以包括耦合到多个位线的多个存储器单元，其形成具有寄生电容的位线节点。 每个存储器单元可以包括具有保持电流的所需电平的开关器件，以保持电池的导通状态。 电压供应电路和控制器可以与NVRAM器件耦合。 控制器可以控制电路以提供使存储器单元处于导通状态的电流脉冲。 响应于在实现设定点之后通过存储器单元的位线节点电容的放电，脉冲可以包括随时间从设定点改变到保持电流电平的分布。 可以描述和/或要求保护其他实施例。

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