公开(公告)号：US20190332278A1

公开(公告)日：2019-10-31

申请号：US16428802

申请日：2019-05-31

Applicant: Intel Corporation

Inventor： Rajesh Sundaram ,  Albert Fazio ,  Derchang Kau ,  Shekoufeh Qawami

IPC: G06F3/06 ,  G11C13/00 ,  G06F13/16 ,  G06F12/02

Abstract: Cross point memory architectures, devices, systems, and methods are disclosed and described, and can include a cross point memory core subsystem having increased bandwidth that is scalable. The memory core can include a plurality of independently operating partitions, each comprising a plurality of cross point memory arrays.

公开(公告)号：US20220415892A1

公开(公告)日：2022-12-29

申请号：US17358073

申请日：2021-06-25

Applicant: INTEL CORPORATION

Inventor： Wilfred Gomes ,  Abhishek A. Sharma ,  Conor P. Puls ,  Mauro J. Kobrinsky ,  Kevin J. Fischer ,  Derchang Kau ,  Albert Fazio ,  Tahir Ghani

IPC: H01L27/105

Abstract: Integrated circuit (IC) devices with stacked two-level backend memory, and associated systems and methods, are disclosed. An example IC device includes a front end of line (FEOL) layer, including frontend transistors, and a back end of line (BEOL) layer above the FEOL layer. The BEOL layer includes a first memory layer with memory cells of a first type, and a second memory layer with memory cells of a second type. The first memory layer may be between the FEOL layer and the second memory layer, thus forming stacked backend memory. Stacked backend memory architecture may allow significantly increasing density of memory cells in a memory array having a given footprint area, or, conversely, reducing the footprint area of the memory array with a given memory cell density. Implementing two different types of backend memory may advantageously increase functionality and performance of backend memory.

公开(公告)号：US20220405005A1

公开(公告)日：2022-12-22

申请号：US17349592

申请日：2021-06-16

Applicant: Intel Corporation

Inventor： Scott Weber ,  Jawad Khan ,  Ilya Ganusov ,  Martin Langhammer ,  Matthew Adiletta ,  Terence Magee ,  Albert Fazio ,  Richard Coulson ,  Ravi Gutala ,  Aravind Dasu ,  Mahesh Iyer

IPC: G06F3/06

Abstract: A three dimensional circuit system includes a first integrated circuit die having a core logic region that has first memory circuits and logic circuits. The three dimensional circuit system includes a second integrated circuit die that has second memory circuits. The first and second integrated circuit dies are coupled together in a vertically stacked configuration. The three dimensional circuit system includes third memory circuits coupled to the first integrated circuit die. The third memory circuits reside in a plane of the first integrated circuit die. The logic circuits are coupled to access the first, second, and third memory circuits and data can move between the first, second, and third memories. The third memory circuits have a larger memory capacity and a smaller memory access bandwidth than the second memory circuits. The second memory circuits have a larger memory capacity and a smaller memory access bandwidth than the first memory circuits.

公开(公告)号：US11010061B2

公开(公告)日：2021-05-18

申请号：US16428802

申请日：2019-05-31

Applicant: Intel Corporation

Inventor： Rajesh Sundaram ,  Albert Fazio ,  Derchang Kau ,  Shekoufeh Qawami

IPC: G06F12/00 ,  G06F3/06 ,  G06F13/16 ,  G06F12/02 ,  G11C13/00

Abstract: Cross point memory architectures, devices, systems, and methods are disclosed and described, and can include a cross point memory core subsystem having increased bandwidth that is scalable. The memory core can include a plurality of independently operating partitions, each comprising a plurality of cross point memory arrays.

公开(公告)号：US10679698B2

公开(公告)日：2020-06-09

申请号：US15939026

申请日：2018-03-28

Applicant: Intel Corporation

Inventor： Prashant S. Damle ,  Wei Fang ,  Albert Fazio

IPC: G11C11/00 ,  G11C13/00 ,  G06F13/40 ,  G06F13/16 ,  G11C29/02 ,  G11C29/50 ,  G11C29/52 ,  G11C29/44 ,  G11C29/04

Abstract: A memory device includes a memory array having multiple nonvolatile memory cells that stores data as a set or a reset state of the memory cells. The nonvolatile memory cells can be resistance-based memory, which stores data based on resistive state of the memory cells. A controller coupled to the memory array periodically samples set and reset margins for memory cells of the memory array. Responsive to detection of a change in a margin, the system can adaptively adjust a preset electrical setting used to differentiate between a set state and a reset state.

公开(公告)号：US20180088834A1

公开(公告)日：2018-03-29

申请号：US15281006

申请日：2016-09-29

Applicant: Intel Corporation

Inventor： Rajesh Sundaram ,  Albert Fazio ,  Derchang Kau ,  Shekoufeh Qawami

IPC: G06F3/06

CPC classification number: G06F3/0613 ,  G06F3/0644 ,  G06F3/0659 ,  G06F3/0688 ,  G06F12/0238 ,  G06F12/0246 ,  G06F13/16 ,  G06F13/1657 ,  G11C13/0004

Abstract: Cross point memory architectures, devices, systems, and methods are disclosed and described, and can include a cross point memory core subsystem having increased bandwidth that is scalable. The memory core can include a plurality of independently operating partitions, each comprising a plurality of cross point memory arrays.

公开(公告)号：US11789641B2

公开(公告)日：2023-10-17

申请号：US17349592

申请日：2021-06-16

Applicant: Intel Corporation

Inventor： Scott Weber ,  Jawad Khan ,  Ilya Ganusov ,  Martin Langhammer ,  Matthew Adiletta ,  Terence Magee ,  Albert Fazio ,  Richard Coulson ,  Ravi Gutala ,  Aravind Dasu ,  Mahesh Iyer

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/061 ,  G06F3/0673

Abstract: A three dimensional circuit system includes a first integrated circuit die having a core logic region that has first memory circuits and logic circuits. The three dimensional circuit system includes a second integrated circuit die that has second memory circuits. The first and second integrated circuit dies are coupled together in a vertically stacked configuration. The three dimensional circuit system includes third memory circuits coupled to the first integrated circuit die. The third memory circuits reside in a plane of the first integrated circuit die. The logic circuits are coupled to access the first, second, and third memory circuits and data can move between the first, second, and third memories. The third memory circuits have a larger memory capacity and a smaller memory access bandwidth than the second memory circuits. The second memory circuits have a larger memory capacity and a smaller memory access bandwidth than the first memory circuits.

公开(公告)号：US10331360B2

公开(公告)日：2019-06-25

申请号：US15281006

申请日：2016-09-29

Applicant: Intel Corporation

Inventor： Rajesh Sundaram ,  Albert Fazio ,  Derchang Kau ,  Shekoufeh Qawami

IPC: G06F12/00 ,  G06F3/06 ,  G06F13/16 ,  G06F12/02 ,  G11C13/00

Abstract: Cross point memory architectures, devices, systems, and methods are disclosed and described, and can include a cross point memory core subsystem having increased bandwidth that is scalable. The memory core can include a plurality of independently operating partitions, each comprising a plurality of cross point memory arrays.