公开(公告)号：US09235256B2

公开(公告)日：2016-01-12

申请号：US14227680

申请日：2014-03-27

Applicant: INTEL CORPORATION

Inventor： Andrew Herdrich ,  Ramesh Illikkal ,  Donald Newell ,  Ravishankar Iyer ,  Vineet Chadha

IPC: G06F1/00 ,  G06F1/26 ,  G06F1/32 ,  G06F9/46 ,  G06F9/50 ,  G06F12/08

CPC classification number: G06F9/44505 ,  G06F1/10 ,  G06F1/32 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3296 ,  G06F9/50 ,  G06F9/5094 ,  G06F12/0891 ,  Y02D10/128

Abstract: An apparatus comprises a plurality of cores and a controller coupled to the cores. The controller is to lower an operating point of a first core if a first number based on processor clock cycles per instruction (CPI) associated with a second core is higher than a first threshold. The controller is operable to increase the operating point of the first core if the first number is lower than a second threshold.

公开(公告)号：US08924748B2

公开(公告)日：2014-12-30

申请号：US14141992

申请日：2013-12-27

Applicant: Intel Corporation

Inventor： Andrew Herdrich ,  Ramesh Illikkal ,  Donald Newell ,  Ravishankar Iyer ,  Vineet Chadha

IPC: G06F1/00 ,  G06F1/26 ,  G06F1/32 ,  G06F9/46 ,  G06F9/50 ,  G06F12/08

CPC classification number: G06F9/44505 ,  G06F1/10 ,  G06F1/32 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3296 ,  G06F9/50 ,  G06F9/5094 ,  G06F12/0891 ,  Y02D10/128

Abstract: An apparatus comprises a plurality of cores and a controller coupled to the cores. The controller is to lower an operating point of a first core if a first number based on processor clock cycles per instruction (CPI) associated with a second core is higher than a first threshold. The controller is operable to increase the operating point of the first core if the first number is lower than a second threshold.

公开(公告)号：US20200328973A1

公开(公告)日：2020-10-15

申请号：US16870991

申请日：2020-05-10

Applicant: Intel Corporation

Inventor： Srihari Makineni ,  Ravi Iyer ,  Dave Minturn ,  Sujoy Sen ,  Donald Newell ,  Li Zhao

IPC: H04L12/741 ,  H04L29/06 ,  H04L12/931

Abstract: In general, in one aspect, the disclosures describes a method that includes receiving multiple ingress Internet Protocol packets, each of the multiple ingress Internet Protocol packets having an Internet Protocol header and a Transmission Control Protocol segment having a Transmission Control Protocol header and a Transmission Control Protocol payload, where the multiple packets belonging to a same Transmission Control Protocol/Internet Protocol flow. The method also includes preparing an Internet Protocol packet having a single Internet Protocol header and a single Transmission Control Protocol segment having a single Transmission Control Protocol header and a single payload formed by a combination of the Transmission Control Protocol segment payloads of the multiple Internet Protocol packets. The method further includes generating a signal that causes receive processing of the Internet Protocol packet.

公开(公告)号：US20150095675A1

公开(公告)日：2015-04-02

申请号：US14564436

申请日：2014-12-09

Applicant: INTEL CORPORATION

Inventor： Andrew Herdrich ,  Ramesh Illikkal ,  Donald Newell ,  Ravishankar Iyer ,  Vineet Chadha

IPC: G06F1/32

CPC classification number: G06F9/44505 ,  G06F1/10 ,  G06F1/32 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3296 ,  G06F9/50 ,  G06F9/5094 ,  G06F12/0891 ,  Y02D10/128

Abstract: An apparatus comprises a plurality of cores and a controller coupled to the cores. The controller is to lower an operating point of a first core if a first number based on processor clock cycles per instruction (CPI) associated with a second core is higher than a first threshold. The controller is operable to increase the operating point of the first core if the first number is lower than a second threshold.

Abstract translation: 一种装置包括多个核心和耦合到核心的控制器。 如果基于与第二核心相关联的每个指令（CPI）的处理器时钟周期的第一数量高于第一阈值，则控制器将降低第一核心的工作点。 如果第一数量低于第二阈值，则控制器可操作以增加第一核心的工作点。