公开(公告)号：US10748603B2

公开(公告)日：2020-08-18

申请号：US16146473

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Huseyin Ekin Sumbul ,  Gregory K. Chen ,  Raghavan Kumar ,  Phil Knag ,  Abhishek Sharma ,  Sasikanth Manipatruni ,  Amrita Mathuriya ,  Ram Krishnamurthy ,  Ian A. Young

IPC: G11C8/00 ,  G11C11/418 ,  G06F9/30 ,  G11C11/419 ,  G11C13/00 ,  G11C7/10 ,  G11C11/54 ,  G06N3/063 ,  G06N3/08 ,  G11C7/18 ,  G06F7/544 ,  G11C11/16

Abstract: A memory circuit has compute-in-memory circuitry that enables a multiply-accumulate (MAC) operation based on shared charge. Row access circuitry drives multiple rows of a memory array to multiply a first data word with a second data word stored in the memory array. The row access circuitry drives the multiple rows based on the bit pattern of the first data word. Column access circuitry drives a column of the memory array when the rows are driven. Accessed rows discharge the column line in an accumulative fashion. Sensing circuitry can sense voltage on the column line. A processor in the memory circuit computes a MAC value based on the voltage sensed on the column.

公开(公告)号：US10713558B2

公开(公告)日：2020-07-14

申请号：US15395231

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： Huseyin Ekin Sumbul ,  Gregory K. Chen ,  Raghavan Kumar ,  Phil Knag ,  Ram K. Krishnamurthy

IPC: G06N3/04 ,  G06N3/063 ,  G06N3/08

Abstract: In one embodiment, a method comprises determining that a membrane potential of a first neuron of a first neuron core exceeds a threshold; determining a first plurality of synapse cores that each store at least one synapse weight associated with the first neuron; and sending a spike message to the determined first plurality of synapse cores.

公开(公告)号：US20180189631A1

公开(公告)日：2018-07-05

申请号：US15395231

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： Huseyin Ekin Sumbul ,  Gregory K. Chen ,  Raghavan Kumar ,  Phil Knag ,  Ram K. Krishnamurthy

IPC: G06N3/04 ,  G06N3/08

CPC classification number: G06N3/04 ,  G06N3/049 ,  G06N3/063 ,  G06N3/08

Abstract: In one embodiment, a method comprises determining that a membrane potential of a first neuron of a first neuron core exceeds a threshold; determining a first plurality of synapse cores that each store at least one synapse weight associated with the first neuron; and sending a spike message to the determined first plurality of synapse cores.

公开(公告)号：US11812599B2

公开(公告)日：2023-11-07

申请号：US17670248

申请日：2022-02-11

Applicant: Intel Corporation

Inventor： Abhishek Sharma ,  Noriyuki Sato ,  Sarah Atanasov ,  Huseyin Ekin Sumbul ,  Gregory K. Chen ,  Phil Knag ,  Ram Krishnamurthy ,  Hui Jae Yoo ,  Van H. Le

IPC: G11C8/00 ,  H10B12/00 ,  H01L27/12 ,  G11C11/4096

CPC classification number: H10B12/00 ,  G11C11/4096 ,  H01L27/124 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/1255 ,  H01L27/1266

Abstract: Examples herein relate to a memory device comprising an eDRAM memory cell, the eDRAM memory cell can include a write circuit formed at least partially over a storage cell and a read circuit formed at least partially under the storage cell; a compute near memory device bonded to the memory device; a processor; and an interface from the memory device to the processor. In some examples, circuitry is included to provide an output of the memory device to emulate output read rate of an SRAM memory device comprises one or more of: a controller, a multiplexer, or a register. Bonding of a surface of the memory device can be made to a compute near memory device or other circuitry. In some examples, a layer with read circuitry can be bonded to a layer with storage cells. Any layers can be bonded together using techniques described herein.

公开(公告)号：US11727260B2

公开(公告)日：2023-08-15

申请号：US17484828

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Abhishek Sharma ,  Jack T. Kavalieros ,  Ian A. Young ,  Ram Krishnamurthy ,  Sasikanth Manipatruni ,  Uygar Avci ,  Gregory K. Chen ,  Amrita Mathuriya ,  Raghavan Kumar ,  Phil Knag ,  Huseyin Ekin Sumbul ,  Nazila Haratipour ,  Van H. Le

IPC: G06N3/063 ,  H01L27/108 ,  H01L27/11502 ,  G06N3/04 ,  G06F17/16 ,  H01L27/11 ,  G11C11/54 ,  G11C7/10 ,  G11C11/419 ,  G11C11/409 ,  G11C11/22 ,  G06N3/065 ,  H10B10/00 ,  H10B12/00 ,  H10B53/00

CPC classification number: G06N3/065 ,  G06F17/16 ,  G06N3/04 ,  G11C7/1006 ,  G11C7/1039 ,  G11C11/54 ,  H10B10/18 ,  H10B12/01 ,  H10B12/033 ,  H10B12/20 ,  H10B12/50 ,  H10B53/00 ,  G11C11/221 ,  G11C11/409 ,  G11C11/419

Abstract: An apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The memory array includes an embedded dynamic random access memory (eDRAM) memory array. Another apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The mathematical computation circuit includes a switched capacitor circuit. The switched capacitor circuit includes a back-end-of-line (BEOL) capacitor coupled to a thin film transistor within the metal/dielectric layers of the semiconductor chip. Another apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The mathematical computation circuit includes an accumulation circuit. The accumulation circuit includes a ferroelectric BEOL capacitor to store a value to be accumulated with other values stored by other ferroelectric BEOL capacitors.

公开(公告)号：US10922607B2

公开(公告)日：2021-02-16

申请号：US15394976

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： Abhronil Sengupta ,  Gregory K. Chen ,  Raghavan Kumar ,  Huseyin Ekin Sumbul ,  Phil Knag

IPC: G06N3/08 ,  G06N3/04

Abstract: In one embodiment, a processor is to store a membrane potential of a neural unit of a neural network; and calculate, at a particular time-step of the neural network, a change to the membrane potential of the neural unit occurring over multiple time-steps that have elapsed since the last time-step at which the membrane potential was updated, wherein each of the multiple time-steps that have elapsed since the last time-step is associated with at least one input to the neural unit that affects the membrane potential of the neural unit.

公开(公告)号：US10831446B2

公开(公告)日：2020-11-10

申请号：US16145569

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Gregory K. Chen ,  Raghavan Kumar ,  Huseyin Ekin Sumbul ,  Phil Knag ,  Ram Krishnamurthy ,  Sasikanth Manipatruni ,  Amrita Mathuriya ,  Abhishek Sharma ,  Ian A. Young

IPC: G06F7/544 ,  G06F17/16 ,  G06F7/501 ,  G06F9/30 ,  G06N3/04 ,  G06N3/063

Abstract: A memory device that includes a plurality subarrays of memory cells to store static weights and a plurality of digital full-adder circuits between subarrays of memory cells is provided. The digital full-adder circuit in the memory device eliminates the need to move data from a memory device to a processor to perform machine learning calculations. Rows of full-adder circuits are distributed between sub-arrays of memory cells to increase the effective memory bandwidth and reduce the time to perform matrix-vector multiplications in the memory device by performing bit-serial dot-product primitives in the form of accumulating m 1-bit×n-bit multiplications.

公开(公告)号：US20190197391A1

公开(公告)日：2019-06-27

申请号：US15855813

申请日：2017-12-27

Applicant: Intel Corporation

Inventor： Gregory Kengho Chen ,  Phil Christopher Knag ,  Ram Kumar Krishnamurthy ,  Raghavan Kumar ,  Huseyin Ekin Sumbul

IPC: G06N3/04 ,  G06N3/063 ,  G06N3/08

CPC classification number: G06N3/049 ,  G06N3/063 ,  G06N3/08

Abstract: Systems and methods may apply homeostatic plasticity control in a spiking neural network, such as at a neuron of a core of the spiking neural network. The neuron may receive input spike information and determine whether to activate an output spike at the neuron based at least in part on the input spike information and a bias value. The bias value may be set based on whether the neuron issued a previous output spike during a previous time period. The bias value may be updated based on whether the output spike was activated at the neuron. For example, in accordance with a determination to activate the output spike, the bias value may be decreased, and in accordance with a determination to not activate the output spike, the bias value may be increased.

公开(公告)号：US20190043560A1

公开(公告)日：2019-02-07

申请号：US16146473

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Huseyin Ekin Sumbul ,  Gregory K. Chen ,  Raghavan Kumar ,  Phil Knag ,  Abhishek Sharma ,  Sasikanth Manipatruni ,  Amrita Mathuriya ,  Ram Krishnamurthy ,  Ian A. Young

IPC: G11C11/418 ,  G06F7/544 ,  G06F9/30 ,  G11C13/00 ,  G11C11/419

Abstract: A memory circuit has compute-in-memory circuitry that enables a multiply-accumulate (MAC) operation based on shared charge. Row access circuitry drives multiple rows of a memory array to multiply a first data word with a second data word stored in the memory array. The row access circuitry drives the multiple rows based on the bit pattern of the first data word. Column access circuitry drives a column of the memory array when the rows are driven. Accessed rows discharge the column line in an accumulative fashion. Sensing circuitry can sense voltage on the column line. A processor in the memory circuit computes a MAC value based on the voltage sensed on the column.

公开(公告)号：US20190042910A1

公开(公告)日：2019-02-07

申请号：US15845245

申请日：2017-12-18

Applicant: Intel Corporation

Inventor： Ram Kumar Krishnamurthy ,  Gregory Kengho Chen ,  Raghavan Kumar ,  Phil Christopher Knag ,  Huseyin Ekin Sumbul

IPC: G06N3/04

Abstract: System and techniques for spike timing dependent plasticity (STDP) in neuromorphic hardware are described herein. A first spike may be received, at a first neuron at a first time, from a second neuron. The first neuron may produce a second spike at a second time after the first time. At a third time after the second time, the first neuron may receive a third spike from the second neuron. Here, the third spike is a replay of the first spike with a defined time offset. The first neuron may then perform long term potentiation (LTP) for the first spike using the third spike.