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    Traffic class arbitration based on priority and bandwidth allocation
    11.
    发明授权
    Traffic class arbitration based on priority and bandwidth allocation 有权

    公开(公告)号：US10715452B2

    公开(公告)日：2020-07-14

    申请号：US16259228

    申请日：2019-01-28

    Applicant: Intel Corporation

    Inventor： Albert S. Cheng ,  Thomas D. Lovett ,  Michael A. Parker

    IPC: H04L12/851 ,  H04L12/931 ,  H04L12/911 ,  H04L12/26 ,  H04L12/715 ,  H04L12/841

    Abstract: This disclosure describes systems, devices, methods and computer readable media for enhanced network communication for use in higher performance applications including storage, high performance computing (HPC) and Ethernet-based fabric interconnects. In some embodiments, a network controller may include a transmitter circuit configured to transmit packets on a plurality of virtual lanes (VLs), the VLs associated with a defined VL priority and an allocated share of network bandwidth. The network controller may also include a bandwidth monitor module configured to measure bandwidth consumed by the packets and an arbiter module configured to adjust the VL priority based on a comparison of the measured bandwidth to the allocated share of network bandwidth. The transmitter circuit may be further configured to transmit the packets based on the adjusted VL priority.

    Technologies for adaptive routing using network traffic characterization
    12.
    发明授权
    Technologies for adaptive routing using network traffic characterization 有权

    公开(公告)号：US10389636B2

    公开(公告)日：2019-08-20

    申请号：US15200449

    申请日：2016-07-01

    Applicant: Intel Corporation

    Inventor： Mario Flajslik ,  Eric R. Borch ,  Michael A. Parker

    IPC: H04L12/801 ,  H04L12/26 ,  H04L12/935 ,  H04L12/931 ,  H04L12/947

    Abstract: Technologies for adaptive routing based on network traffic pattern characterization include a network switch configured to receive a network packet via one of a plurality of input ports and identify a set of the plurality of output ports associated with a path usable to forward the received network packet to a destination computing device along. The network switch is further configured to adjust a total congestion value for each of the set of output ports based on a type of the path to which each of the set of output ports corresponds and a value of a minimal path counter to which each of the set of output ports corresponds and enqueue the received network packet into an output buffer queue of one of the set of output ports based on the total congestion value. Other embodiments are described herein.

    TECHNOLOGIES FOR EFFICIENTLY DETERMINING A ROOT OF CONGESTION WITH A MULTI-STAGE NETWORK SWITCH
    13.
    发明申请
    TECHNOLOGIES FOR EFFICIENTLY DETERMINING A ROOT OF CONGESTION WITH A MULTI-STAGE NETWORK SWITCH 审中-公开

    公开(公告)号：US20190007317A1

    公开(公告)日：2019-01-03

    申请号：US15639864

    申请日：2017-06-30

    Applicant: Intel Corporation

    Inventor： Albert S. Cheng ,  Michael A. Parker

    IPC: H04L12/801 ,  H04L12/835 ,  H04L12/26

    Abstract: Technologies for determining a root of congestion include a network switch. The network switch is to operate arbiter units in at least one upstream stage at a packet transfer rate that is greater than a packet transfer rate of an arbiter unit in an output stage, determine whether an input buffer of a remote network switch in communication with the output stage has sustained congestion over a first predefined time period, determine whether an output buffer of the arbiter unit in the output stage has sustained congestion over a second predefined time period, and determine, as a function of whether the input buffer of the remote network switch has sustained congestion and whether the output buffer of the arbiter unit in the output stage has sustained congestion, whether the network switch is a root of congestion.

    Fast data center congestion response
    17.
    发明授权
    Fast data center congestion response 有权

    公开(公告)号：US11153211B2

    公开(公告)日：2021-10-19

    申请号：US15836850

    申请日：2017-12-09

    Applicant: Intel Corporation

    Inventor： Vignesh Trichy Ravi ,  Ravi Murty ,  Ravindra Babu Ganapathi ,  Michael A. Parker

    IPC: H04W4/00 ,  H04L12/801 ,  H04L12/835 ,  H04L12/851 ,  H04L12/825

    Abstract: There is included in one example a switch, including: an ingress port to receive data from a source host; a first egress port to send data to a destination host; a second egress port to send data to the source host; and a congestion notification generator (CNG) including: a congestion detector to compute bandwidth consumption of a flow associated with a packet received on the ingress port and assigned to the first egress port, and determine based on the computed bandwidth consumption that the flow is congested; a flow extractor to extract a flow identifier of the flow from the packet; a throttle calculator to calculate a quantitative flow throttle value for the flow; and a header builder to build a congestion notification packet to instruct the source host to throttle the flow.

    Technologies for scalable hierarchical interconnect topologies
    19.
    发明授权
    Technologies for scalable hierarchical interconnect topologies 有权

    公开(公告)号：US10394738B2

    公开(公告)日：2019-08-27

    申请号：US15279830

    申请日：2016-09-29

    Applicant: Intel Corporation

    Inventor： Mario Flajslik ,  Eric R. Borch ,  Michael A. Parker ,  Wayne A. Downer

    IPC: G06F13/40

    Abstract: Technologies for a system of communicatively coupled network switches in a hierarchical interconnect network topology include two or more groups that each include two or more first and second level switches in which each of the first level switches are communicatively coupled to each of the plurality of second level switches to form a complete bipartite graph. Additionally, each of the groups is interconnected to each of the other groups via a corresponding global link connecting a second level switch of one group to a corresponding second level switch of another group. Further, each of the first level switches are communicatively coupled to one or more computing nodes. Other embodiments are described herein.

    TECHNOLOGIES FOR BALANCING THROUGHPUT ACROSS INPUT PORTS OF A MULTI-STAGE NETWORK SWITCH
    20.
    发明申请
    TECHNOLOGIES FOR BALANCING THROUGHPUT ACROSS INPUT PORTS OF A MULTI-STAGE NETWORK SWITCH 审中-公开

    公开(公告)号：US20190007319A1

    公开(公告)日：2019-01-03

    申请号：US15639816

    申请日：2017-06-30

    Applicant: Intel Corporation

    Inventor： Scott S. Diesing ,  Michael A. Parker ,  Albert S. Cheng ,  Nan Ni

    IPC: H04L12/803

    Abstract: Technologies for balancing throughput across input ports include a network switch. The network switch is to generate, for an arbiter unit in a first stage of a hierarchy of stages of arbiter units, turn data indicative of a set of turns in which to transfer packet data from devices connected to input ports of the arbiter unit. The network switch is also to transfer, with the arbiter unit, the packet data from the devices in the set of turns. Additionally, the network switch is to determine weight data indicative of the number of turns represented in the set and provide the weight data from the arbiter unit in the first stage to another arbiter unit in a subsequent stage to cause the arbiter unit in the subsequent stage to allocate a number of turns for the transfer of the packet data from the arbiter unit in the first stage.

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