公开(公告)号：US10771404B2

公开(公告)日：2020-09-08

申请号：US15388604

申请日：2016-12-22

Applicant: Intel Corporation

Inventor： David Keppel ,  Thomas D. Lovett ,  Michael A. Parker ,  Robert C. Zak, Jr.

IPC: H04L12/879 ,  H04L12/26

Abstract: Particular embodiments described herein provide for a network element that can be configured to receive a request message, wherein the request message includes a read trigger, an indicator selector, and a completion trigger, determine an indicator that relates to the indicator selector, and perform an action when the read trigger is activated.

公开(公告)号：US10715452B2

公开(公告)日：2020-07-14

申请号：US16259228

申请日：2019-01-28

Applicant: Intel Corporation

Inventor： Albert S. Cheng ,  Thomas D. Lovett ,  Michael A. Parker

IPC: H04L12/851 ,  H04L12/931 ,  H04L12/911 ,  H04L12/26 ,  H04L12/715 ,  H04L12/841

Abstract: This disclosure describes systems, devices, methods and computer readable media for enhanced network communication for use in higher performance applications including storage, high performance computing (HPC) and Ethernet-based fabric interconnects. In some embodiments, a network controller may include a transmitter circuit configured to transmit packets on a plurality of virtual lanes (VLs), the VLs associated with a defined VL priority and an allocated share of network bandwidth. The network controller may also include a bandwidth monitor module configured to measure bandwidth consumed by the packets and an arbiter module configured to adjust the VL priority based on a comparison of the measured bandwidth to the allocated share of network bandwidth. The transmitter circuit may be further configured to transmit the packets based on the adjusted VL priority.

公开(公告)号：US10454850B2

公开(公告)日：2019-10-22

申请号：US15531694

申请日：2014-12-24

Applicant: Intel Corporation

Inventor： Albert S. Cheng ,  Thomas D. Lovett ,  Michael S. Parker ,  Steven F. Hoover

IPC: H04L12/933 ,  H04L12/935 ,  H04L12/861 ,  H04L12/64 ,  H04L12/937 ,  H04L12/931

Abstract: Apparatuses, methods and storage medium associated with buffering data in a switch are provided. In embodiments, the switch may include a plurality of queue buffers, a plurality of queues respectively associated with the plurality of queue buffers, a shared buffer, and a queue point controller coupled with the plurality of queue buffers and the shared buffer. In embodiments the queue point controller may be configured to determine an amount of available space in a selected queue buffer of the plurality of queue buffers. The queue point controller may be further configured to allocate at least a portion of the shared buffer to a selected queue that is associated with the selected queue buffer. In embodiments, this allocation may be based on the amount of available space determined in the selected queue buffer. Other embodiments may be described and/or claimed.

公开(公告)号：US20180183732A1

公开(公告)日：2018-06-28

申请号：US15388604

申请日：2016-12-22

Applicant: Intel Corporation

Inventor： David Keppel ,  Thomas D. Lovett ,  Michael A. Parker ,  Robert C. Zak, JR.

IPC: H04L12/879 ,  H04L12/26

CPC classification number: H04L49/901 ,  H04L43/022 ,  H04L43/08 ,  H04L43/10 ,  H04L43/16

Abstract: Particular embodiments described herein provide for a network element that can be configured to receive a request message, wherein the request message includes a read trigger, an indicator selector, and a completion trigger, determine an indicator that relates to the indicator selector, and perform an action when the read trigger is activated.

公开(公告)号：US11528229B2

公开(公告)日：2022-12-13

申请号：US16929064

申请日：2020-07-14

Applicant: Intel Corporation

Inventor： Albert S. Cheng ,  Thomas D. Lovett ,  Michael A. Parker

IPC: H04L47/24 ,  H04L47/2425 ,  H04L49/356 ,  H04L47/70 ,  H04L43/0894 ,  H04L45/64 ,  H04L47/283

Abstract: This disclosure describes systems, devices, methods and computer readable media for enhanced network communication for use in higher performance applications including storage, high performance computing (HPC) and Ethernet-based fabric interconnects. In some embodiments, a network controller may include a transmitter circuit configured to transmit packets on a plurality of virtual lanes (VLs), the VLs associated with a defined VL priority and an allocated share of network bandwidth. The network controller may also include a bandwidth monitor module configured to measure bandwidth consumed by the packets and an arbiter module configured to adjust the VL priority based on a comparison of the measured bandwidth to the allocated share of network bandwidth. The transmitter circuit may be further configured to transmit the packets based on the adjusted VL priority.

公开(公告)号：US10205667B2

公开(公告)日：2019-02-12

申请号：US15614455

申请日：2017-06-05

Applicant: Intel Corporation

Inventor： Ilango Ganga ,  Alain Gravel ,  Thomas D. Lovett ,  Radia Perlman ,  Greg Regnier ,  Anil Vasudevan ,  Hugh Wilkinson

IPC: H04L12/851

Abstract: One embodiment provides a method for enabling class-based credit flow control for a network node in communication with a link partner using an Ethernet communications protocol. The method includes receiving a control frame from the link partner. The control frame includes at least one field for specifying credit for at least one traffic class and the credit is based on available space in a receive buffer associated with the at least one traffic class. The method further includes sending data packets to the link partner based on the credit, the data packets associated with the at least one traffic class.

公开(公告)号：US09917787B2

公开(公告)日：2018-03-13

申请号：US15184375

申请日：2016-06-16

Applicant: Intel Corporation

Inventor： Todd Rimmer ,  Thomas D. Lovett ,  Albert Cheng

IPC: H04L12/801 ,  H04L12/919 ,  H04L12/925 ,  H04L12/933 ,  H04L12/861 ,  G06F13/42 ,  H04L12/931 ,  H04L12/851 ,  G06F5/06 ,  G06F13/16

CPC classification number: H04L47/39 ,  G06F5/065 ,  G06F13/1673 ,  G06F13/4221 ,  G06F2205/067 ,  H04L47/2408 ,  H04L47/2433 ,  H04L47/245 ,  H04L47/30 ,  H04L47/722 ,  H04L47/765 ,  H04L49/103 ,  H04L49/109 ,  H04L49/358 ,  H04L49/505 ,  H04L49/70 ,  H04L49/9057

Abstract: Method, apparatus, and systems for implementing flexible credit exchange within high performance fabrics. Available buffer space in a receive buffer on a receive-side of a link is managed and tracked at the transmit-side of the link using credits. Peer link interfaces coupled via a link are provided with receive buffer configuration information that specifies how the receive buffer space in each peer is partitioned and space allocated for each buffer, including a plurality of virtual lane (VL) buffers. Credits are used for tracking buffer space consumption and in credits are returned from the receive-side indicating freed buffer space. The peer link interfaces exchange credit organization information to inform the other peer of how much space each credit represents. In connection with data transfer over the link, the transmit-side de-allocates credits based on an amount of buffer space to be consumed in applicable buffers in the receive buffer. Upon space being freed in the receive buffer, the receive-side returns credit ACKnowledgements (ACKs) identifying a VL for which space has been freed.

公开(公告)号：US09648148B2

公开(公告)日：2017-05-09

申请号：US14139930

申请日：2013-12-24

Applicant: Intel Corporation

Inventor： Todd Rimmer ,  Thomas D. Lovett ,  Albert Cheng

IPC: H04L29/06 ,  H04L12/851 ,  H04L12/801 ,  H04L12/933 ,  H04L12/805 ,  H04L12/931

CPC classification number: H04L47/2425 ,  H04L47/2408 ,  H04L47/2458 ,  H04L47/2491 ,  H04L49/10 ,  H04L49/3045 ,  H04L49/358 ,  H04L49/70 ,  H04L69/22

Abstract: Method, apparatus, and systems for implementing Quality of Service (QoS) within high performance fabrics. A multi-level QoS scheme is implemented including virtual fabrics, Traffic Classes, Service Levels (SLs), Service Channels (SCs) and Virtual Lanes (VLs). SLs are implemented for Layer 4 (Transport Layer) end-to-end transfer of fabric packets, while SCs are used to differentiate fabric packets at the Link Layer. Fabric packets are divided into flits, with fabric packet data transmitted via fabric links as flits streams. Fabric switch input ports and device receive ports detect SC IDs for received fabric packets and implement SC-to-VL mappings to determine VL buffers to buffer fabric packet flits in. An SL may have multiple SCs, and SC-to-SC mapping may be implemented to change the SC for a fabric packet as it is forwarded through the fabric, while maintaining its SL. A Traffic Class may include multiple SLs, enabling request and response traffic for an application to employ separate SLs.

公开(公告)号：US20150222533A1

公开(公告)日：2015-08-06

申请号：US14173782

申请日：2014-02-05

Applicant: INTEL CORPORATION

Inventor： Mark S. Birrittella ,  Thomas D. Lovett ,  Todd Rimmer

IPC: H04L12/721 ,  H04L12/947 ,  H04L12/741

CPC classification number: H04L45/745 ,  H04L5/0055 ,  H04L45/66 ,  H04L45/74 ,  H04L47/17 ,  H04L47/39 ,  H04L49/25 ,  H04L61/3075 ,  H04Q2213/13215

Abstract: Method, apparatus, and systems for reliably transferring Ethernet packet data over a link layer and facilitating fabric-to-Ethernet and Ethernet-to-fabric gateway operations at matching wire speed and packet data rate. Ethernet header and payload data is extracted from Ethernet frames received at the gateway and encapsulated in fabric packets to be forwarded to a fabric endpoint hosting an entity to which the Ethernet packet is addressed. The fabric packets are divided into flits, which are bundled in groups to form link packets that are transferred over the fabric at the Link layer using a reliable transmission scheme employing implicit ACKnowledgements. At the endpoint, the fabric packet is regenerated, and the Ethernet packet data is de-encapsulated. The Ethernet frames received from and transmitted to an Ethernet network are encoded using 64b/66b encoding, having an overhead-to-data bit ratio of 1:32. Meanwhile, the link packets have the same ratio, including one overhead bit per flit and a 14-bit CRC plus a 2-bit credit return field or sideband used for credit-based flow control.

Abstract translation: 用于通过链路层可靠地传输以太网分组数据的方法，装置和系统，并且以匹配的线速度和分组数据速率促进以太网和以太网到网络的网关操作。 从网关接收的以太网帧提取以太网报头和有效载荷数据，并将其封装在结构数据包中，以转发到托管以太网数据包所针对的实体的结构端点。 结构分组被划分成flits，它们被分组成组，以形成通过使用隐式确认的可靠传输方案在链路层上通过结构传送的链路分组。 在端点，重新生成Fabric数据包，并对以太网数据包进行解封装。 从以太网网络接收并发送到以太网的以太网帧使用64b / 66b编码进行编码，具有1:32的开销数据比特率。 同时，链路分组具有相同的比率，包括一个开销比特每个flit和一个14比特CRC加上一个2比特的信用回报字段或用于基于信用的流量控制的边带。

公开(公告)号：US10757039B2

公开(公告)日：2020-08-25

申请号：US15531688

申请日：2014-12-24

Applicant: Intel Corporation

Inventor： Albert S. Cheng ,  Thomas D. Lovett ,  Michael A. Parker

IPC: H04L12/947 ,  H04L12/835 ,  H04L12/741 ,  H04L12/801 ,  H04L12/935 ,  H04L12/933 ,  H04L12/803

Abstract: Apparatuses, methods and storage medium associated with routing data in a switch are provided. In embodiments, the switch may include route lookup circuitry determine a first set of output ports that are available to send a data packet to a destination node. The lookup circuitry may further select, based on respective congestion levels associated with the first set of output ports, a plurality of output ports for a second set of output ports from the first set of output ports. An input queue of the switch may buffer the data packet and route information associated with the second set of output ports. The switch may further include route selection circuitry to select a destination output port from the second set of output ports, based on updated congestion levels associated with the output ports of the second set of output ports. Other embodiments may be described and/or claimed.