公开(公告)号：US11171207B2

公开(公告)日：2021-11-09

申请号：US16647695

申请日：2017-12-20

Applicant: INTEL CORPORATION

Inventor： Willy Rachmady ,  Cheng-Ying Huang ,  Matthew V. Metz ,  Nicholas G. Minutillo ,  Sean T. Ma ,  Anand S. Murthy ,  Jack T. Kavalieros ,  Tahir Ghani ,  Gilbert Dewey

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/205 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: A transistor includes a body of semiconductor material with a gate structure in contact with a portion of the body. A source region contacts the body adjacent the gate structure and a drain region contacts the body adjacent the gate structure such that the portion of the body is between the source region and the drain region. A first isolation region is under the source region and has a top surface in contact with a bottom surface of the source region. A second isolation region is under the drain region and has a top surface in contact with a bottom surface of the drain region. Depending on the transistor configuration, a major portion of the inner-facing sidewalls of the first and second isolation regions contact respective sidewalls of either a subfin structure (e.g., FinFET transistor configurations) or a lower portion of a gate structure (e.g., gate-all-around transistor configuration).

公开(公告)号：US20200279916A1

公开(公告)日：2020-09-03

申请号：US16647695

申请日：2017-12-20

Applicant: INTEL CORPORATION

Inventor： Willy Rachmady ,  Cheng-Ying Huang ,  Matthew V. Metz ,  Nicholas G. Minutillo ,  Sean T. Ma ,  Anand S. Murthy ,  Jack T. Kavalieros ,  Tahir Ghani ,  Gilbert Dewey

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78 ,  H01L29/205 ,  H01L29/66

Abstract: A transistor includes a body of semiconductor material with a gate structure in contact with a portion of the body. A source region contacts the body adjacent the gate structure and a drain region contacts the body adjacent the gate structure such that the portion of the body is between the source region and the drain region. A first isolation region is under the source region and has a top surface in contact with a bottom surface of the source region. A second isolation region is under the drain region and has a top surface in contact with a bottom surface of the drain region. Depending on the transistor configuration, a major portion of the inner-facing sidewalls of the first and second isolation regions contact respective sidewalls of either a subfin structure (e.g., FinFET transistor configurations) or a lower portion of a gate structure (e.g., gate-all-around transistor configuration).

公开(公告)号：US12288808B2

公开(公告)日：2025-04-29

申请号：US18370586

申请日：2023-09-20

Applicant: Intel Corporation

Inventor： Ryan Keech ,  Anand S. Murthy ,  Nicholas G. Minutillo ,  Suresh Vishwanath ,  Mohammad Hasan ,  Biswajeet Guha ,  Subrina Rafique

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/10 ,  H01L29/167 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78

Abstract: Integrated circuit structures having source or drain structures with abrupt dopant profiles are described. In an example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires. A second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal nanowires. The first and second epitaxial source or drain structures include silicon, phosphorous and arsenic, with an atomic concentration of phosphorous substantially the same as an atomic concentration of arsenic.

公开(公告)号：US11923410B2

公开(公告)日：2024-03-05

申请号：US17493695

申请日：2021-10-04

Applicant: Intel Corporation

Inventor： Willy Rachmady ,  Cheng-Ying Huang ,  Matthew V. Metz ,  Nicholas G. Minutillo ,  Sean T. Ma ,  Anand S. Murthy ,  Jack T. Kavalieros ,  Tahir Ghani ,  Gilbert Dewey

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/205 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L29/0653 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/205 ,  H01L29/42392 ,  H01L29/785

Abstract: A transistor includes a body of semiconductor material, where the body has laterally opposed body sidewalls and a top surface. A gate structure contacts the top surface of the body. A source region contacts a first one of the laterally opposed body sidewalls and a drain region contacts a second one of the laterally opposed body sidewalls. A first isolation region is under the source region and has a top surface in contact with a bottom surface of the source region. A second isolation region is under the drain region and has a top surface in contact with a bottom surface of the drain region. Depending on the transistor configuration, a major portion of the inner-facing sidewalls of the first and second isolation regions contact respective sidewalls of either a subfin structure (e.g., FinFET transistor configurations) or a lower portion of a gate structure (e.g., gate-all-around transistor configuration).

公开(公告)号：US11804523B2

公开(公告)日：2023-10-31

申请号：US16580941

申请日：2019-09-24

Applicant: Intel Corporation

Inventor： Ryan Keech ,  Anand S. Murthy ,  Nicholas G. Minutillo ,  Suresh Vishwanath ,  Mohammad Hasan ,  Biswajeet Guha ,  Subrina Rafique

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/167 ,  H01L29/417 ,  H01L29/10

CPC classification number: H01L29/0847 ,  H01L29/0673 ,  H01L29/1037 ,  H01L29/167 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/785

Abstract: Integrated circuit structures having source or drain structures with abrupt dopant profiles are described. In an example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires. A second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal nanowires. The first and second epitaxial source or drain structures include silicon, phosphorous and arsenic, with an atomic concentration of phosphorous substantially the same as an atomic concentration of arsenic.

公开(公告)号：US20200287024A1

公开(公告)日：2020-09-10

申请号：US16649592

申请日：2017-12-27

Applicant: INTEL CORPORATION

Inventor： Gilbert Dewey ,  Sean T. Ma ,  Tahir Ghani ,  Willy Rachmady ,  Cheng-Ying Huang ,  Anand S. Murthy ,  Harold W. Kennel ,  Nicholas G. Minutillo ,  Matthew V. Metz

IPC: H01L29/66 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78

Abstract: Transistors having a plurality of channel semiconductor structures, such as fins, over a dielectric material. A source and drain are coupled to opposite ends of the structures and a gate stack intersects the plurality of structures between the source and drain. Lateral epitaxial overgrowth (LEO) may be employed to form a super-lattice of a desired periodicity from a sidewall of a fin template structure that is within a trench and extends from the dielectric material. Following LEO, the super-lattice structure may be planarized with surrounding dielectric material to expose a top of the super-lattice layers. Alternating ones of the super-lattice layers may then be selectively etched away, with the retained layers of the super-lattice then laterally separated from each other by a distance that is a function of the super-lattice periodicity. A gate dielectric and a gate electrode may be formed over the retained super-lattice layers for a channel of a transistor.

公开(公告)号：US20200006501A1

公开(公告)日：2020-01-02

申请号：US16490504

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Willy Rachmady ,  Sean T. Ma ,  Matthew V. Metz ,  Nicholas G. Minutillo ,  Cheng-Ying Huang ,  Dewey Gilbert ,  Jack T. Kavalieros ,  Anand S. Murthy ,  Tahir Ghani

IPC: H01L29/40 ,  H01L27/092 ,  H01L29/78 ,  H01L29/10 ,  H01L29/66 ,  H01L21/8252

Abstract: Solid-state assemblies including dielectric lining layers having localized charges are provided. Processes to form the solid-state assemblies also are provided. The solid-state assemblies can included in CMOS transistors, where first dielectric lining layers having localized charges of positive polarity can be adjacent to the PMOS member and a second dielectric lining layers having localized charges of positive polarity can be adjacent to an NMOS member. The first dielectric lining layers can be adjacent to a first gate electrode of the CMOS transistor, and the second dielectric lining can be adjacent to a second gate electrode of the CMOS transistor. The first dielectric lining layers and the second dielectric lining layers can improve, at least in part, the performance of the CMOS transistor by attracting mobile carriers into respective transport channels of the PMOS member and the NMOS member.