公开(公告)号：US12107085B2

公开(公告)日：2024-10-01

申请号：US18219374

申请日：2023-07-07

申请人： Intel Corporation

发明人： Aaron D. Lilak ,  Gilbert Dewey ,  Cheng-Ying Huang ,  Christopher Jezewski ,  Ehren Mannebach ,  Rishabh Mehandru ,  Patrick Morrow ,  Anand S. Murthy ,  Anh Phan ,  Willy Rachmady

IPC分类号： H01L27/088 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/8258 ,  H01L21/84 ,  H01L23/00 ,  H01L23/48 ,  H01L23/522 ,  H01L23/538 ,  H01L27/06 ,  H01L27/092

CPC分类号： H01L27/0886 ,  H01L21/76898 ,  H01L21/8258 ,  H01L21/845 ,  H01L23/481 ,  H01L23/5226 ,  H01L24/29 ,  H01L24/32 ,  H01L27/0924 ,  H01L24/94 ,  H01L2224/29188 ,  H01L2224/32145

摘要： Stacked transistor structures having a conductive interconnect between source/drain regions of upper and lower transistors. In some embodiments, the interconnect is provided, at least in part, by highly doped epitaxial material deposited in the upper transistor's source/drain region. In such cases, the epitaxial material seeds off of an exposed portion of semiconductor material of or adjacent to the upper transistor's channel region and extends downward into a recess that exposes the lower transistor's source/drain contact structure. The epitaxial source/drain material directly contacts the lower transistor's source/drain contact structure, to provide the interconnect. In other embodiments, the epitaxial material still seeds off the exposed semiconductor material of or proximate to the channel region and extends downward into the recess, but need not contact the lower contact structure. Rather, a metal-containing contact structure passes through the epitaxial material of the upper source/drain region and contacts the lower transistor's source/drain contact structure.

公开(公告)号：US20240204060A1

公开(公告)日：2024-06-20

申请号：US18065660

申请日：2022-12-14

申请人： Intel Corporation

发明人： Rohit Galatage ,  Cheng-Ying Huang ,  Jack T. Kavalieros ,  Marko Radosavljevic ,  Mauro J. Kobrinsky ,  Jami Wiedemer ,  Munzarin Qayyum ,  Evan Clinton

IPC分类号： H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC分类号： H01L29/401 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/6653 ,  H01L29/66742 ,  H01L29/775 ,  H01L2029/42388

摘要： IC structures with nanoribbon stacks without dielectric protection caps for top nanoribbons, and associated methods and devices, are disclosed. An example IC structure includes a stack of nanoribbons, an opening over the top nanoribbon of the stack of nanoribbons, and a gate electrode material in the opening, where the opening has a first portion, a second portion, and a third portion, the second portion is between the first portion and the third portion, and where a width of a portion of the gate electrode material in the second portion is smaller than a width of a portion of the gate electrode material in the first portion. In such an IC structure, a gate insulator on the sidewalls of the first portion of the opening is materially discontinuous from a gate insulator on the sidewalls of the third portion of the opening.

公开(公告)号：US11996411B2

公开(公告)日：2024-05-28

申请号：US16913796

申请日：2020-06-26

申请人： Intel Corporation

发明人： Cheng-Ying Huang ,  Gilbert Dewey ,  Anh Phan ,  Nicole K. Thomas ,  Urusa Alaan ,  Seung Hoon Sung ,  Christopher M. Neumann ,  Willy Rachmady ,  Patrick Morrow ,  Hui Jae Yoo ,  Richard E. Schenker ,  Marko Radosavljevic ,  Jack T. Kavalieros ,  Ehren Mannebach

IPC分类号： H01L29/78 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H10B12/00

CPC分类号： H01L27/0924 ,  H01L29/0673 ,  H01L29/4232 ,  H01L29/775 ,  H01L29/7851 ,  H10B12/056

摘要： Embodiments disclosed herein include stacked forksheet transistor devices, and methods of fabricating stacked forksheet transistor devices. In an example, an integrated circuit structure includes a backbone. A first transistor device includes a first vertical stack of semiconductor channels adjacent to an edge of the backbone. A second transistor device includes a second vertical stack of semiconductor channels adjacent to the edge of the backbone. The second transistor device is stacked on the first transistor device.

公开(公告)号：US11996404B2

公开(公告)日：2024-05-28

申请号：US17540120

申请日：2021-12-01

申请人： Intel Corporation

发明人： Cheng-Ying Huang ,  Gilbert Dewey ,  Ashish Agrawal ,  Kimin Jun ,  Willy Rachmady ,  Zachary Geiger ,  Cory Bomberger ,  Ryan Keech ,  Koustav Ganguly ,  Anand Murthy ,  Jack Kavalieros

IPC分类号： H01L27/06 ,  H01L21/683 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/04 ,  H01L29/08 ,  H01L29/10

CPC分类号： H01L27/0688 ,  H01L21/6835 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823857 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/1033 ,  H01L2221/68363

摘要： A monolithic three-dimensional integrated circuit may include multiple transistor levels separated by one or more levels of metallization. An upper level transistor structure may include a monocrystalline channel material over a bottom gate stack. The channel material and the gate stack materials may be formed on a donor substrate at any suitable temperature, and subsequently transferred from the donor substrate to a host substrate that includes lower-level circuitry. The upper-level transistor may be patterned from the transferred layers so that the gate electrode includes one or more bonding layers. Source and drain material may be patterned from a source and drain material layer that was transferred from the donor substrate along with the channel material, or source and drain material may be grown at low temperatures from the transferred channel material.

公开(公告)号：US11923370B2

公开(公告)日：2024-03-05

申请号：US17030226

申请日：2020-09-23

申请人： Intel Corporation

发明人： Seung Hoon Sung ,  Cheng-Ying Huang ,  Marko Radosavljevic ,  Christopher M. Neumann ,  Susmita Ghose ,  Varun Mishra ,  Cory Weber ,  Stephen M. Cea ,  Tahir Ghani ,  Jack T. Kavalieros

IPC分类号： H01L27/12 ,  H01L21/84

CPC分类号： H01L27/1203 ,  H01L21/84

摘要： Embodiments disclosed herein include forksheet transistor devices having a dielectric or a conductive spine. For example, an integrated circuit structure includes a dielectric spine. A first transistor device includes a first vertical stack of semiconductor channels spaced apart from a first edge of the dielectric spine. A second transistor device includes a second vertical stack of semiconductor channels spaced apart from a second edge of the dielectric spine. An N-type gate structure is on the first vertical stack of semiconductor channels, a portion of the N-type gate structure laterally between and in contact with the first edge of the dielectric spine and the first vertical stack of semiconductor channels. A P-type gate structure is on the second vertical stack of semiconductor channels, a portion of the P-type gate structure laterally between and in contact with the second edge of the dielectric spine and the second vertical stack of semiconductor channels.

公开(公告)号：US11830933B2

公开(公告)日：2023-11-28

申请号：US16240369

申请日：2019-01-04

申请人： Intel Corporation

发明人： Willy Rachmady ,  Gilbert Dewey ,  Jack T. Kavalieros ,  Aaron Lilak ,  Patrick Morrow ,  Anh Phan ,  Cheng-Ying Huang ,  Ehren Mannebach

IPC分类号： H01L29/00 ,  H01L29/66 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

CPC分类号： H01L29/66742 ,  H01L21/02236 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823892 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/78696

摘要： Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures using a bottom-up oxidation approach, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires above a substrate. The vertical arrangement of nanowires has one or more active nanowires above one or more oxidized nanowires. A gate stack is over the vertical arrangement of nanowires and around the one or more oxidized nanowires.

公开(公告)号：US11784239B2

公开(公告)日：2023-10-10

申请号：US16341020

申请日：2016-12-14

申请人： Intel Corporation

发明人： Sean T. Ma ,  Aaron D. Lilak ,  Justin R. Weber ,  Harold W. Kennel ,  Willy Rachmady ,  Gilbert W. Dewey ,  Cheng-Ying Huang ,  Matthew V. Metz ,  Jack T. Kavalieros ,  Anand S. Murthy ,  Tahir Ghani

IPC分类号： H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L29/40

CPC分类号： H01L29/66795 ,  H01L29/0665 ,  H01L29/408 ,  H01L29/785 ,  H01L29/7855

摘要： Disclosed herein are tri-gate transistor arrangements, and related methods and devices. For example, in some embodiments, a transistor arrangement may include a fin stack shaped as a fin extending away from a base, and a subfin dielectric stack. The fin includes a subfin portion and a channel portion, the subfin portion being closer to the base than the channel portion. The subfin dielectric stack includes a transistor dielectric material, and a fixed charge liner material disposed between the transistor dielectric material and the subfin portion of the fin.

公开(公告)号：US20230197815A1

公开(公告)日：2023-06-22

申请号：US17556750

申请日：2021-12-20

申请人： Intel Corporation

发明人： Cheng-Ying Huang ,  Patrick Morrow ,  Gilbert Dewey ,  Willy Rachmady ,  Nicole K. Thomas ,  Marko Radosavljevic ,  Jack T. Kavalieros

IPC分类号： H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L27/088

CPC分类号： H01L29/42392 ,  H01L29/0665 ,  H01L29/78618 ,  H01L27/088

摘要： Techniques to form wrap-around contacts in a stacked transistor architecture. An example includes a first source or drain region and a second source or drain region spaced from and over the first source or drain region. A conductive contact is on a top surface of the second source or drain and extends down one or more side surfaces of the second source or drain region such that the conductive contact is laterally adjacent to a bottom surface of the second source or drain region. In some cases, the conductive contact is also on a top surface of the first source or drain region, and/or extends down a side surface of the first source or drain region. In some cases, a second conductive contact is on a bottom surface of the first source or drain region, and may extend up a side surface the first source or drain region.

公开(公告)号：US20230145229A1

公开(公告)日：2023-05-11

申请号：US17522342

申请日：2021-11-09

申请人： Intel Corporation

发明人： Nicole K. Thomas ,  Ashish Agrawal ,  Gilbert Dewey ,  Cheng-Ying Huang ,  Ehren Mannebach ,  Willy Rachmady ,  Marko Radosavljevic

IPC分类号： H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L27/088

CPC分类号： H01L29/42392 ,  H01L29/0665 ,  H01L29/78696 ,  H01L27/088

摘要： Techniques are provided herein to form semiconductor devices having backside contacts. Sacrificial plugs are formed first within a substrate at particular locations to align with source and drain regions during a later stage of processing. Another wafer is subsequently bonded to the surface of the substrate and is thinned to effectively transfer different material layers to the top surface of the substrate. One of the transferred layers acts as a seed layer for the growth of additional semiconductor material used to form semiconductor devices. The source and drain regions of the semiconductor devices are sufficiently aligned over the previously formed sacrificial plugs. A backside portion of the substrate may be removed to expose the sacrificial plugs from the backside. Removal of the plugs and replacement of the recesses left behind with conductive material forms the conductive backside contacts to the source or drain regions.

公开(公告)号：US20230134379A1

公开(公告)日：2023-05-04

申请号：US17517925

申请日：2021-11-03

申请人： Intel Corporation

发明人： Cheng-Ying Huang ,  Urusa Alaan ,  Susmita Ghose ,  Rambert Nahm ,  Natalie Briggs ,  Nicole K. Thomas ,  Willy Rachmady ,  Marko Radosavljevic ,  Jack T. Kavalieros

IPC分类号： H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/8234

摘要： Techniques are provided herein to form gate-all-around (GAA) semiconductor devices, such as those having a stacked transistor configuration. In one example case, two different semiconductor devices may both be GAA transistors each having any number of nanoribbons extending in the same (e.g., horizontal) direction where one device is located vertically above the other device. An internal spacer structure extends between the nanoribbons of both devices along the vertical direction, where the spacer structure includes one or more rib features between the two devices. A gate structure that includes one or more gate dielectric layers and one or more gate electrode layers may be formed around the nanoribbons of both devices, in some cases. In other cases, a split-gate configuration is used where upper and lower gate structures are separated by an isolation structure. Forksheet transistors and other GAA configurations may be formed using the techniques as well.