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11.
公开(公告)号:US20220114495A1
公开(公告)日:2022-04-14
申请号:US17558284
申请日:2021-12-21
Applicant: Intel Corporation
Inventor: Eriko Nurvitadhi , Rajesh Poornachandran , Abhijit Davare , Nilesh Jain , Chaunte Lacewell , Anahita Bhiwandiwalla , Juan Pablo Munoz , Andrew Boutros , Yash Akhauri
Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed for composable machine learning compute nodes. An example apparatus includes interface circuitry to receive a workload, instructions in the apparatus, and processor circuitry to at least one of execute or instantiate the instructions to generate a first configuration of one or more machine-learning models based on a workload, generate a second configuration of hardware, determine an evaluation parameter based on an execution of the workload, the execution of the workload based on the first configuration and the second configuration, and, in response to the evaluation parameter satisfying a threshold, execute the one or more machine-learning models in the first configuration on the hardware in the second configuration, the one or more machine-learning models and the hardware to execute the workload.
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公开(公告)号:US20220108054A1
公开(公告)日:2022-04-07
申请号:US17552955
申请日:2021-12-16
Applicant: Intel Corporation
Inventor: Yash Akhauri , Nilesh Jain , Juan Pablo Munoz Chiabrando , Adithya M. Niranjan
IPC: G06F30/27
Abstract: An architecture search system evaluates a search space of neural network and hardware architectures with a plurality of candidate controllers. Each controller attempts to identify an optimized architecture using a different optimization algorithm. To identify a controller for the search space, the architecture search system samples subspaces of the search space having a portion of the neural network search space and a portion of the hardware search space. For each subspace, candidate controllers are scored with respect to the optimized design determined by the respective candidate controllers. Using the scores for the various candidate controllers across the sampled subspaces, a controller is selected to optimize the overall network architecture search space.
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公开(公告)号:US20170185900A1
公开(公告)日:2017-06-29
申请号:US14998235
申请日:2015-12-26
Applicant: INTEL CORPORATION
Inventor: Arnab Paul , Nilesh Jain , Hsiang-Tsung Kung
CPC classification number: G06N20/00
Abstract: An apparatus is described herein. The apparatus includes a clustering mechanism that is to partition a dictionary into a plurality of clusters. The apparatus also includes a feature-matching mechanism that is to pre-compute feature matching results for each cluster of the plurality of clusters. Moreover, the apparatus includes a selector that is to locate a best representative feature from the dictionary in response to an input vector.
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公开(公告)号:US20250124105A1
公开(公告)日:2025-04-17
申请号:US19002132
申请日:2024-12-26
Applicant: Intel Corporation
Inventor: Gopi Krishna Jha , Sameh Gobriel , Nilesh Jain
IPC: G06F17/16
Abstract: Key-value (KV) caching accelerates inference in large language models (LLMs) by allowing the attention operation to scale linearly rather than quadratically with the total sequence length. Due to large context lengths in modern LLMs, KV cache size can exceed the model size, which can negatively impact throughput. To address this issue, KVCrush, which stands for KEY-VALUE CACHE SIZE REDUCTION USING SIMILARITY IN HEAD-BEHAVIOR, is implemented. KVCrush involves using binary vectors to represent tokens, where the vector indicates which attention heads attend to the token and which attention heads disregard the token. The binary vectors are used in a hardware-efficient, low-overhead process to produce representatives for unimportant tokens to be pruned, without having to implement k-means clustering techniques.
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公开(公告)号:US20250055987A1
公开(公告)日:2025-02-13
申请号:US18812760
申请日:2024-08-22
Applicant: Intel Corporation
Inventor: Brinda Ganesh , Nilesh Jain , Sumit Mohan , Faouzi Kossentini , Jill Boyce , James Holland , Zhijun Lei , Chekib Nouira , Foued Ben Amara , Hassene Tmar , Sebastian Possos , Craig Hurst
IPC: H04N19/114 , H04N19/154
Abstract: Techniques related to distributing the video encoding processing of an input video across hardware and software systems. Such techniques include evaluating the content of the video and determine whether or the encoding operation is best to be done on the hardware system only, software system only or a hybrid hardware and software system.
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公开(公告)号:US20240311950A1
公开(公告)日:2024-09-19
申请号:US18478233
申请日:2023-09-29
Applicant: Intel Corporation
Inventor: Selvakumar Panneer , Nilesh Jain , SungYe Kim
Abstract: Described herein is a graphics processor configured to perform time based frame generation via a temporally aware machine learning model that enables the generation of a frame at a target timestamp relative to the render times of input frames. For example, for an extrapolated frame generated by the temporally aware machine learning model, a low relative timestamp would indicate that the extrapolated frame will appear close in time after the final frame in a sequence of frames and should be relatively close in appearance to the final frame. A higher relative timestamp would indicate that the extrapolated frame should depict a greater degree of evolution based on the optical flow.
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17.
公开(公告)号:US20240144030A1
公开(公告)日:2024-05-02
申请号:US18279820
申请日:2022-06-08
Applicant: Intel Corporation
Inventor: Juan Pablo Muñoz , Nilesh Jain , Chaunté Lacewell , Alexander Kozlov , Nikolay Lyalyushkin , Vasily Shamporov , Anastasia Senina
IPC: G06N3/0985
CPC classification number: G06N3/0985
Abstract: Methods, apparatus, systems, and articles of manufacture to modify pre-trained models to apply neural architecture search are disclosed. Example instructions, when executed, cause processor circuitry to at least access a pre-trained machine learning model, create a super-network based on the pre-trained machine learning model, create a plurality of subnetworks based on the super-network, and search the plurality of subnetworks to select a subnetwork.
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18.
公开(公告)号:US20240045685A1
公开(公告)日:2024-02-08
申请号:US17958381
申请日:2022-10-01
Applicant: Intel Corporation
Inventor: Menachem Adelman , Amit Gradstein , Alexander Heinecke , Christopher Hughes , Naveen Mellempudi , Shahar Mizrahi , Dana Rip , Simon Rubanovich , Uri Sherman , Guy Boudoukh , Evangelos Georganas , Nilesh Jain , Barukh Ziv
IPC: G06F9/30
CPC classification number: G06F9/30145 , G06F9/30025 , G06F9/3001
Abstract: Systems, methods, and apparatuses relating sparsity based FMA. In some examples, an instance of a single FMA instruction has one or more fields for an opcode, one or more fields to identify a source/destination matrix operand, one or more fields to identify a first plurality of source matrix operands, one or more fields to identify a second plurality of matrix operands, wherein the opcode is to indicate that execution circuitry is to select a proper subset of FP8 data elements from the first plurality of source matrix operands based on sparsity controls from a first matrix operand of the second plurality of matrix operands and perform a FMA.
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公开(公告)号:US11637687B2
公开(公告)日:2023-04-25
申请号:US16723743
申请日:2019-12-20
Applicant: Intel Corporation
Inventor: Ned Smith , Francesc Guim Bernat , Sanjay Bakshi , Paul O'Neill , Ben McCahill , Brian A. Keating , Adrian Hoban , Kapil Sood , Mona Vij , Nilesh Jain , Rajesh Poornachandran , Trevor Cooper , Kshitij A. Doshi , Marcin Spoczynski
Abstract: Methods, apparatus, systems and articles of manufacture to determine provenance for data supply chains are disclosed. Example instructions cause a machine to at least, in response to data being generated, generate a local data object and object metadata corresponding to the data; hash the local data object; generate a hash of a label of the local data object; generate a hierarchical data structure for the data including the hash of the local data object and the hash of the label of the local data object; generate a data supply chain object including the hierarchical data structure; and transmit the data and the data supply chain object to a device that requested access to the data.
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公开(公告)号:US11557085B2
公开(公告)日:2023-01-17
申请号:US17112792
申请日:2020-12-04
Applicant: Intel Corporation
Inventor: Jill Boyce , Soethiha Soe , Selvakumar Panneer , Adam Lake , Nilesh Jain , Deepak Vembar , Glen J. Anderson , Varghese George , Carl Marshall , Scott Janus , Saurabh Tangri , Karthik Veeramani , Prasoonkumar Surti
Abstract: Embodiments are directed to neural network processing for multi-object three-dimensional (3D) modeling. An embodiment of a computer-readable storage medium includes executable computer program instructions for obtaining data from multiple cameras, the data including multiple images, and generating a 3D model for 3D imaging based at least in part on the data from the cameras, wherein generating the 3D model includes one or more of performing processing with a first neural network to determine temporal direction based at least in part on motion of one or more objects identified in an image of the multiple images or performing processing with a second neural network to determine semantic content information for an image of the multiple images.
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