公开(公告)号：US20180321936A1

公开(公告)日：2018-11-08

申请号：US15943609

申请日：2018-04-02

Applicant: Intel Corporation

Inventor： Edward Grochowski ,  Hong Wang ,  John P. Shen ,  Perry H. Wang ,  Jamison D. Collins ,  James Held ,  Partha Kundu ,  Raya Leviathan ,  Tin-Fook Ngai

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30003 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/30101 ,  G06F9/3013 ,  G06F9/384 ,  G06F9/3851

Abstract: A method and system to provide user-level multithreading are disclosed. The method according to the present techniques comprises receiving programming instructions to execute one or more shared resource threads (shreds) via an instruction set architecture (ISA). One or more instruction pointers are configured via the ISA; and the one or more shreds are executed simultaneously with a microprocessor, wherein the microprocessor includes multiple instruction sequencers.

公开(公告)号：US20180307484A1

公开(公告)日：2018-10-25

申请号：US15900030

申请日：2018-02-20

Applicant: Intel Corporation

Inventor： Ed Grochowski ,  Hong Wang ,  John P. Shen ,  Perry H. Wang ,  Jamison D. Collins ,  James Held ,  Partha Kundu ,  Raya Leviathan ,  Tin-Fook Ngai

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30003 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/30101 ,  G06F9/3013 ,  G06F9/384 ,  G06F9/3851

Abstract: A method and system to provide user-level multithreading are disclosed. The method according to the present techniques comprises receiving programming instructions to execute one or more shared resource threads (shreds) via an instruction set architecture (ISA). One or more instruction pointers are configured via the ISA; and the one or more shreds are executed simultaneously with a microprocessor, wherein the microprocessor includes multiple instruction sequencers.

公开(公告)号：US09529715B2

公开(公告)日：2016-12-27

申请号：US13843890

申请日：2013-03-15

Applicant: Intel Corporation

Inventor： Sanjeev Kumar ,  Christopher J. Hughes ,  Partha Kundu ,  Anthony Nguyen

IPC: G06F12/08 ,  G06F9/46 ,  G06F9/52 ,  G06F9/30 ,  G06F9/38

CPC classification number: G06F12/0806 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30087 ,  G06F9/30145 ,  G06F9/3834 ,  G06F9/3857 ,  G06F9/3859 ,  G06F9/467 ,  G06F9/528 ,  G06F12/0831 ,  G06F12/084 ,  G06F12/0848 ,  G06F2212/60 ,  G06F2212/621

Abstract: Embodiments of the invention relate a hybrid hardware and software implementation of transactional memory accesses in a computer system. A processor including a transactional cache and a regular cache is utilized in a computer system that includes a policy manager to select one of a first mode (a hardware mode) or a second mode (a software mode) to implement transactional memory accesses. In the hardware mode the transactional cache is utilized to perform read and write memory operations and in the software mode the regular cache is utilized to perform read and write memory operations.

公开(公告)号：US09442721B2

公开(公告)日：2016-09-13

申请号：US13722481

申请日：2012-12-20

Applicant: Intel Corporation

Inventor： Edward T. Grochowski ,  Hong Wang ,  John P. Shen ,  Perry H. Wang ,  Jamison D. Colins ,  James P. Held ,  Partha Kundu ,  Raya Leviathan ,  Tin-Fook Ngai

IPC: G06F9/30 ,  G06F9/54 ,  G06F9/38

CPC classification number: G06F9/30003 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/30101 ,  G06F9/3013 ,  G06F9/384 ,  G06F9/3851

Abstract: A method and system to provide user-level multithreading are disclosed. The method according to the present techniques comprises receiving programming instructions to execute one or more shared resource threads (shreds) via an instruction set architecture (ISA). One or more instruction pointers are configured via the ISA; and the one or more shreds are executed simultaneously with a microprocessor, wherein the microprocessor includes multiple instruction sequencers.

Abstract translation: 公开了提供用户级多线程的方法和系统。 根据本技术的方法包括接收经由指令集架构（ISA）执行一个或多个共享资源线程（碎片）的编程指令。 一个或多个指令指针通过ISA配置; 并且一个或多个碎片与微处理器同时执行，其中微处理器包括多个指令定序器。