公开(公告)号：US20190042152A1

公开(公告)日：2019-02-07

申请号：US15833955

申请日：2017-12-06

Applicant: Intel Corporation

Inventor： Sanjeev N. TRIKA ,  Peng LI ,  Jawad B. KHAN ,  Myron LOEWEN

IPC: G06F3/06 ,  G06F11/07 ,  H04L29/08

Abstract: Examples include techniques for implementing a write transaction to two or more memory devices in a storage device. In some examples, the write transaction includes an atomic write transaction from an application or operating system executing on a computing platform to a storage device coupled with the computing platform. For these examples, the storage device includes a storage controller to receive an atomic multimedia write transaction request to write first data and second data; cause the first data to be stored in a first memory device, and cause the second data to be stored in a second memory device, simultaneously and atomically.

公开(公告)号：US20210223998A1

公开(公告)日：2021-07-22

申请号：US17222048

申请日：2021-04-05

Applicant: Intel Corporation

Inventor： Peng LI ,  Sanjeev N. TRIKA

IPC: G06F3/06 ,  G06F12/02 ,  G06F1/26

Abstract: Quality of Service of a multi-stream solid state drive is improved by storing data to be written to a NAND die in the solid state drive in a byte-addressable write-in-place non-volatile memory in the solid state drive in the event of a NAND die collision preventing a write to the NAND die. The data stored in the a byte-addressable write-in-place non-volatile memory is written to the NAND die when the NAND die is not busy.

公开(公告)号：US20200185290A1

公开(公告)日：2020-06-11

申请号：US16614765

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： Dinesh PADMANABHAN RAMALEKSHMI THANU ,  Hemanth K. DHAVALESWARAPU ,  Venkata Suresh GUTHIKONDA ,  John J. BEATTY ,  Yonghao AN ,  Marco Aurelio CARTAS AYALA ,  Luke J. GARNER ,  Peng LI

IPC: H01L23/16 ,  H01L23/367 ,  H01L25/16 ,  H01L21/52 ,  H01L23/538 ,  H01L23/498 ,  H01L25/065

Abstract: Semiconductor packages having a sealant bridge between an integrated heat spreader and a package substrate are described. In an embodiment, a semiconductor package includes a sealant bridge anchoring the integrated heat spreader to the package substrate at locations within an overhang gap laterally between a semiconductor die and a sidewall of the integrated heat spreader. The sealant bridge extends between a top wall of the integrated heat spreader and a die side component, such as a functional electronic component or a non-functional component, or a satellite chip on the package substrate. The sealant bridge modulates warpage or stress in thermal interface material joints to reduce thermal degradation of the semiconductor package.

公开(公告)号：US20190079859A1

公开(公告)日：2019-03-14

申请号：US15703907

申请日：2017-09-13

Applicant: INTEL CORPORATION

Inventor： Peng LI ,  Sanjeev N. TRIKA

IPC: G06F12/02 ,  H04L29/08 ,  G11C16/34

Abstract: Provided are an apparatus, computer program product, system, and method for managing multiple regions of a non-volatile memory device. A first group of logical bands is assigned to a first memory region in which metadata will be stored and a second group of logical bands is assigned to a second memory region to which host data is written, wherein the second group of logical bands is larger than the first group of logical bands. Physical bands are mapped to the first number of logical bands and the second number of logical bands. Indication is returned to the host system of the first and second groups of logical bands assigned to the first and second memory regions, respectively. The host system directs requests for metadata to logical addresses in the first group of logical bands and directs request for file data to logical addresses in the second group of logical bands

公开(公告)号：US20190042153A1

公开(公告)日：2019-02-07

申请号：US15857406

申请日：2017-12-28

Applicant: Intel Corporation

Inventor： Jawad B. KHAN ,  Sanjeev N. TRIKA ,  Myron LOEWEN ,  Peng LI

IPC: G06F3/06 ,  G06F12/10

Abstract: A mass storage device controller is described. The controller is to process first and second read requests received at an I/O interface of a mass storage device. The first read request includes a first logical block address. The first read request is to provide a first block stored within non volatile storage media of the mass storage device at the I/O interface. The first block is identified by the first logical block address. The second read request includes a second logical block address and specifies one or more bytes within a second block identified by the second block address and stored within the non volatile storage media. The second read request is to provide the one or more bytes at the I/O interface.

公开(公告)号：US20180234177A1

公开(公告)日：2018-08-16

申请号：US15430053

申请日：2017-02-10

Applicant: INTEL CORPORATION

Inventor： Peng LI

IPC: H04B10/079 ,  H04B10/40

CPC classification number: H04B10/07953 ,  H04B10/071 ,  H04B10/0731 ,  H04B10/077 ,  H04B10/40

Abstract: The present disclosure provides a programmable integrated circuit die for optical testing. The integrated circuit die includes both photonic and electronic elements. In particular, the integrated circuit die may include a memory block, a programmable logic block (for example, a field programmable gate array), an electrical transceiver block, an optical transceiver block, and an optical test interface unit. The programmable logic block may be programmed to have logic functionalities of an embedded microcontroller and of various encoders/decoders. The logic functions may be soft, hard, or mixed. The memory may be used to store test patterns, look-up tables, measured waveforms, error time profiles and statistics. The electrical and optical transceivers may implement PAMn, NRZ, or QAMn modulations and may have programmable parameters, including: voltage levels; optical power; slew rate; magnitude/phase; clock generation and recovery; equalizations; sampling levels; and sampling times. Other embodiments and features are also disclosed.

公开(公告)号：US20210311659A1

公开(公告)日：2021-10-07

申请号：US17350574

申请日：2021-06-17

Applicant: Intel Corporation

Inventor： Peng LI ,  Jawad B. KHAN ,  Sanjeev N. TRIKA

IPC: G06F3/06 ,  G06F12/1081

Abstract: A host-managed storage device includes an offload capability that enables the host to offload all or a portion of a defrag operation to the storage device. Rather than issuing read, write or copy operations and commands to relocate data to the host's DRAM, the host assembles a defrag operation command descriptor for the storage device controller. The command descriptor includes a defrag bitmap that can be directly accessed by the storage device controller to conduct the defrag operation entirely on the storage device at band granularity, without consuming host CPU cycles or host memory. The reduction in host operations/commands achieved by offloading defragmentation to the storage device is on the order of at least a thousand-fold reduction.

公开(公告)号：US20210193548A1

公开(公告)日：2021-06-24

申请号：US16721807

申请日：2019-12-19

Applicant: Intel Corporation

Inventor： Zhimin WAN ,  Chia-Pin CHIU ,  Peng LI ,  Shankar DEVASENATHIPATHY

IPC: H01L23/367 ,  H01L25/065 ,  H01L23/42 ,  H01L23/373 ,  H01L23/538 ,  H01L23/00 ,  H01L25/00 ,  H01L21/56 ,  H01L21/48

Abstract: Embodiments include semiconductor packages and a method to form such packages. A semiconductor package includes first and second bottom dies on a package substrate. The semiconductor package includes first top dies on the first bottom die, second top dies on the second bottom die, and a pedestal on the first and second bottom dies. The pedestal comprises a high thermal conductive material and is positioned on a region of top surfaces of the first and second bottom dies. The semiconductor package includes an encapsulation layer over the first and second bottom dies, and surrounds the first and second top dies and the pedestal. The semiconductor package includes a TIM over the first and second top dies, pedestal, and encapsulation layer, and an integrated heat spreader (IHS) over the TIM. The pedestal is on a periphery region of the top surfaces of the first and second bottom dies.

公开(公告)号：US20190042571A1

公开(公告)日：2019-02-07

申请号：US15973428

申请日：2018-05-07

Applicant: Intel Corporation

Inventor： Peng LI ,  Sanjeev N. TRIKA

IPC: G06F17/30

Abstract: An update-insert (“upsert”) interface manages updates to key-value storage at a memory or storage device. An upsert token is used to store a key and data for a transform to update a previous value stored for a key-value pair. The upsert token processing includes an upsert command to generate the upsert token for an existing key-value pair and store the upsert token in one or more first non-volatile memory (NVM) devices maintained at a memory or storage device. A hash-to-physical (H2P) table or index stored in one or more second NVM devices of the memory or storage device is utilized to locate and read the data for the key and the data for the transform and coalesce the transform(s) into a current value for the key-value pair, thereby avoiding unnecessary read and write amplification when updating key-value storage.

公开(公告)号：US20180173420A1

公开(公告)日：2018-06-21

申请号：US15387600

申请日：2016-12-21

Applicant: INTEL CORPORATION

Inventor： Peng LI ,  William K. LUI ,  Sanjeev N. TRIKA

IPC: G06F3/06 ,  G06F12/10

CPC classification number: G06F3/061 ,  G06F3/0631 ,  G06F3/064 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0665 ,  G06F3/0679 ,  G06F3/068 ,  G06F12/10 ,  G06F2212/1016 ,  G06F2212/152 ,  G06F2212/214 ,  G06F2212/7201 ,  G06F2212/7203

Abstract: Provided are an apparatus, system and method for using a validity table indicating whether physical addresses have valid data to optimize write and defragmentation operations. A non-volatile memory storage device has non-volatile memory and a main memory. A memory controller reads and writes to the non-volatile memory and maintains in the main memory a logical-to-physical address table indicating, for each logical address of a plurality of logical addresses, a physical address in the non-volatile memory having data for the logical address. The main memory maintains a validity table indicating for each physical address of a plurality of physical addresses in the non-volatile memory whether the physical address has valid data.