公开(公告)号：US20240282667A1

公开(公告)日：2024-08-22

申请号：US18635894

申请日：2024-04-15

Applicant: Intel Corporation

Inventor： Weston BERTRAND ,  Kyle ARRINGTON ,  Shankar DEVASENATHIPATHY ,  Aaron MCCANN ,  Nicholas NEAL ,  Zhimin WAN

IPC: H01L23/433 ,  H01L23/367 ,  H01L25/065

CPC classification number: H01L23/433 ,  H01L23/3675 ,  H01L25/0657

Abstract: Embodiments of the present disclosure may generally relate to systems, apparatuses, techniques, and/or processes directed to packages that include stacked dies that use thermal conductivity features including thermally conductive through silicon vias (TSVs) filled with thermally conductive material located in passive areas of a first die to route heat from a first die away from a second die that is coupled with the first die. In embodiments, the first die may be referred to as a base die. Embodiments may include thermal blocks in the form of dummy dies that include TSVs at least partially filled with thermal energy conducting material such as copper, solder, or other alloy.

公开(公告)号：US20230128903A1

公开(公告)日：2023-04-27

申请号：US18088478

申请日：2022-12-23

Applicant: Intel Corporation

Inventor： Weston BERTRAND ,  Kyle ARRINGTON ,  Shankar DEVASENATHIPATHY ,  Aaron MCCANN ,  Nicholas NEAL ,  Zhimin WAN

IPC: H01L23/433 ,  H01L25/065 ,  H01L23/367

Abstract: Embodiments of the present disclosure may generally relate to systems, apparatuses, techniques, and/or processes directed to packages that include stacked dies that use thermal conductivity features including thermally conductive through silicon vias (TSVs) filled with thermally conductive material located in passive areas of a first die to route heat from a first die away from a second die that is coupled with the first die. In embodiments, the first die may be referred to as a base die. Embodiments may include thermal blocks in the form of dummy dies that include TSVs at least partially filled with thermal energy conducting material such as copper, solder, or other alloy.

公开(公告)号：US20210193548A1

公开(公告)日：2021-06-24

申请号：US16721807

申请日：2019-12-19

Applicant: Intel Corporation

Inventor： Zhimin WAN ,  Chia-Pin CHIU ,  Peng LI ,  Shankar DEVASENATHIPATHY

IPC: H01L23/367 ,  H01L25/065 ,  H01L23/42 ,  H01L23/373 ,  H01L23/538 ,  H01L23/00 ,  H01L25/00 ,  H01L21/56 ,  H01L21/48

Abstract: Embodiments include semiconductor packages and a method to form such packages. A semiconductor package includes first and second bottom dies on a package substrate. The semiconductor package includes first top dies on the first bottom die, second top dies on the second bottom die, and a pedestal on the first and second bottom dies. The pedestal comprises a high thermal conductive material and is positioned on a region of top surfaces of the first and second bottom dies. The semiconductor package includes an encapsulation layer over the first and second bottom dies, and surrounds the first and second top dies and the pedestal. The semiconductor package includes a TIM over the first and second top dies, pedestal, and encapsulation layer, and an integrated heat spreader (IHS) over the TIM. The pedestal is on a periphery region of the top surfaces of the first and second bottom dies.

公开(公告)号：US20200176352A1

公开(公告)日：2020-06-04

申请号：US16612340

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： Je-Young CHANG ,  Chandra M. JHA ,  Shankar DEVASENATHIPATHY ,  Feras EID ,  John C. JOHNSON

IPC: H01L23/427 ,  H01L23/26 ,  H01L23/373 ,  H01L23/433 ,  H01L21/48 ,  F28D15/02

Abstract: An integrated circuit die includes a device side and a backside opposite the device side, wherein the backside includes a heat transfer enhancement configuration formed therein or a heat transfer enhancement structure formed thereon each of which enhance a heat transfer area or a boiling nucleation site density over a planar backside surface. A method of forming an integrated circuit assembly includes disposing a heat exchanger on a multi-chip package, the multi-chip package including at least one integrated circuit die including a device side and an opposite backside includes a heat transfer enhancement configuration formed therein or a heat enhancement structure formed thereon; and contacting the backside of the at least one integrated circuit die with water or other cooling fluids, such as a mixture of water and antifreeze, alcohol, inert fluorinated hydrocarbon, helium, and/or other suitable cooling fluid (either liquid or gas).

公开(公告)号：US20210257277A1

公开(公告)日：2021-08-19

申请号：US16794789

申请日：2020-02-19

Applicant: Intel Corporation

Inventor： Weston BERTRAND ,  Kyle ARRINGTON ,  Shankar DEVASENATHIPATHY ,  Aaron MCCANN ,  Nicholas NEAL ,  Zhimin WAN

IPC: H01L23/433 ,  H01L23/367 ,  H01L25/065

Abstract: Embodiments of the present disclosure may generally relate to systems, apparatuses, techniques, and/or processes directed to packages that include stacked dies that use thermal conductivity features including thermally conductive through silicon vias (TSVs) filled with thermally conductive material located in passive areas of a first die to route heat from a first die away from a second die that is coupled with the first die. In embodiments, the first die may be referred to as a base die. Embodiments may include thermal blocks in the form of dummy dies that include TSVs at least partially filled with thermal energy conducting material such as copper, solder, or other alloy.

公开(公告)号：US20200066655A1

公开(公告)日：2020-02-27

申请号：US16611830

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： Feras EID ,  Venkata Suresh R. GUTHIKONDA ,  Shankar DEVASENATHIPATHY ,  Chandra M. JHA ,  Je-Young CHANG ,  Kyle YAZZIE ,  Prasanna RAGHAVAN ,  Pramod MALATKAR

IPC: H01L23/00 ,  H01L23/544 ,  H05K1/02 ,  H05K1/18 ,  H01L25/065 ,  H01L21/50

Abstract: A foundation layer having a stiffener and methods of forming a stiffener are described. One or more dies are formed over the foundation layer. Each die has a front side surface that is electrically coupled to the foundation layer and a back side surface that is opposite from the front side surface. A stiffening layer (or a stiffener) is formed on the back side surface of at least one of the dies. The stiffening layer may be directly coupled to the back side surface of the one or more dies without an adhesive layer. The stiffening layer may include one or more materials, including at least one of a metal, a metal alloy, and a ceramic. The stiffening layer may be formed to reduce warpage based on the foundation layer and the dies. The one or more materials of the stiffening layer can be formed using a cold spray.