公开(公告)号：US20220027278A1

公开(公告)日：2022-01-27

申请号：US17495454

申请日：2021-10-06

Applicant: Intel Corporation

Inventor： Piotr WYSOCKI ,  Francesc GUIM BERNAT ,  John J. BROWNE ,  Pawel ZAK ,  Rafal SZTEJNA ,  Przemyslaw PERYCZ ,  Timothy VERRALL ,  Szymon KONEFAL

IPC: G06F12/0862 ,  G06F9/48

Abstract: Examples include techniques for core-specific metrics collection. Examples include fetching metrics of a core of a multi-core processor from one or more registers responsive to scheduling of an event. The fetched metrics are pushed to a shared memory space of a memory that is accessible to a user-space application and accessible to other cores of the multi-core processor. The user-space application to access the shared memory space to aggregate core-specific metrics associated with at least the core of the multi-core processor and then publish the aggregated core-specific metrics.

公开(公告)号：US20190042146A1

公开(公告)日：2019-02-07

申请号：US16054983

申请日：2018-08-03

Applicant: Intel Corporation

Inventor： Michal WYSOCZANSKI ,  Kapil KARKRA ,  Piotr WYSOCKI ,  Anand S. RAMALINGAM

IPC: G06F3/06 ,  G06F12/02 ,  G06F13/38

Abstract: A storage system includes a NAND storage media and a nonvolatile storage media as a write buffer for the NAND storage media. The write buffer is partitioned, where the partitions are to buffer write data based on a classification of a received write request. Write requests are placed in the write buffer partition with other write requests of the same classification. The partitions have a size at least equal to the size of an erase unit of the NAND storage media. The write buffer flushes a partition once it has an amount of write data equal to the size of the erase unit.

公开(公告)号：US20180095884A1

公开(公告)日：2018-04-05

申请号：US15282478

申请日：2016-09-30

Applicant: INTEL CORPORATION

Inventor： Maciej KAMINSKI ,  Piotr WYSOCKI ,  Slawomir PTAK

IPC: G06F12/0873 ,  G06F3/06 ,  G06F12/0804 ,  G06F12/0868

CPC classification number: G06F12/0873 ,  G06F3/0611 ,  G06F3/0659 ,  G06F3/068 ,  G06F12/0804 ,  G06F12/0868 ,  G06F2212/1024 ,  G06F2212/205 ,  G06F2212/221 ,  G06F2212/2228 ,  G06F2212/224 ,  G06F2212/271 ,  G06F2212/284 ,  G06F2212/3042 ,  G06F2212/305 ,  G06F2212/313

Abstract: An apparatus is described. The apparatus includes a memory controller comprising logic circuitry to implement a mass storage cache in a non volatile region of a system memory. The non volatile region of the system memory is to support execution of program code directly out of the non volatile region system memory.