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    DEADLINE DRIVEN PACKET PRIORITIZATION FOR IP NETWORKS
    1.
    发明申请
    DEADLINE DRIVEN PACKET PRIORITIZATION FOR IP NETWORKS 审中-公开

    公开(公告)号：US20190044857A1

    公开(公告)日：2019-02-07

    申请号：US16047445

    申请日：2018-07-27

    Applicant: Intel Corporation

    Inventor： Grzegorz JERECZEK ,  Maciej Andrzej KOPROWSKI ,  Piotr WYSOCKI

    IPC: H04L12/741 ,  H04L12/851 ,  H04L29/12 ,  H04L12/751

    CPC classification number: H04L45/745 ,  H04L45/02 ,  H04L47/24 ,  H04L47/562 ,  H04L61/2007

    Abstract: Examples may include an apparatus having a packet receiver to receive a packet, the packet including a packet header having a deadline and a destination network node. The apparatus includes a routing table including a current latency for a path to the destination network node for the packet. The apparatus further includes a reprioritization component to get the deadline for delivery of the packet to the destination network node, to set a remaining time for the packet to the deadline minus a current time, to subtract the current latency from the remaining time when the packet is to be routed, and to assign the packet to one of a plurality of deadline bins based at least in part on the remaining time, each deadline bin associated with one of a plurality of transmit queues, the plurality of deadline bins arranged in a deadline priority order from a highest priority to a lowest priority. The apparatus also includes a packet transmitter to transmit packets from the plurality of transmit queues, the plurality of transmit queues being accessed in the deadline priority order.

    METHOD AND APPARATUS TO PERFORM DYNAMICALLY CONTROLLED INTERRUPT COALESCING FOR A SOLID STATE DRIVE
    3.
    发明申请
    METHOD AND APPARATUS TO PERFORM DYNAMICALLY CONTROLLED INTERRUPT COALESCING FOR A SOLID STATE DRIVE 有权

    公开(公告)号：US20210279186A1

    公开(公告)日：2021-09-09

    申请号：US17331101

    申请日：2021-05-26

    Applicant: Intel Corporation

    Inventor： Maksymilian KUNT ,  Piotr WYSOCKI ,  Mariusz BARCZAK

    IPC: G06F13/16

    Abstract: Dynamically controlled interrupt coalescing is performed by enabling interrupt coalescing when the queue depth of the submission queue is high and disabling interrupt coalescing when the queue depth of the submission queue is low to maintain a required quality of service for a solid state drive. The minimum number of completions in the completion queue to trigger an interrupt is modified based on the queue depth of the submission queue. The minimum number of completions is increased when there is an increase in the queue depth of the submission queue and decreased when there is a decrease in the queue depth of the submission queue.

    ERASURE CODING WRITE HOLE CLOSURE FOR SOLID-STATE DRIVE (SSD) ERASURE CODING
    4.
    发明申请
    ERASURE CODING WRITE HOLE CLOSURE FOR SOLID-STATE DRIVE (SSD) ERASURE CODING 审中-公开

    公开(公告)号：US20200264800A1

    公开(公告)日：2020-08-20

    申请号：US16865566

    申请日：2020-05-04

    Applicant: Intel Corporation

    Inventor： Piotr WYSOCKI ,  Sanjeev N. TRIKA ,  Gregory B. TUCKER ,  Jackson ELLIS ,  Jonathan M. HUGHES

    IPC: G06F3/06 ,  G06F9/30

    Abstract: An embodiment of an electronic storage system includes one or more storage drives, at least one or more of the storage drives supporting erasure coding (EC); and a controller including logic to control local access to the one or more storage drives. The controller, in response to a write command, is to for one or more storage drives, allocate an intermediate buffer in the storage drive's non-volatile memory (NVM) to store intermediate data. The controller is to issue commands to a first storage drive to read old data, compute the intermediate data of the first storage drive as XOR of the old data and new data received in the write command, and atomically write the intermediate data of the first storage drive to the intermediate buffer of the first storage drive and write the new data to the first storage drive's NVM. The controller is to read the intermediate data of the first storage drive from the intermediate buffer of the first storage drive. The controller is further to issue commands to one or more EC storage drives to read the old data, compute result data as the old data XOR a galois field coefficient of the one or more EC storage drives multiplied by the intermediate data, and atomically write the old data to the intermediate buffer of the one or more EC storage drives and write the result data to the one or more EC storage drive's NVM. Other embodiments are disclosed and claimed.

    TECHNIQUES TO FACILITATE OUT OF BAND MANAGEMENT IN A VIRTUALIZATION ENVIRONMENT
    7.
    发明申请
    TECHNIQUES TO FACILITATE OUT OF BAND MANAGEMENT IN A VIRTUALIZATION ENVIRONMENT 审中-公开

    公开(公告)号：US20190317796A1

    公开(公告)日：2019-10-17

    申请号：US16454703

    申请日：2019-06-27

    Applicant: Intel Corporation

    Inventor： Maksymilian KUNT ,  Piotr WYSOCKI ,  Slawomir PTAK ,  Kapil KARKRA

    IPC: G06F9/455 ,  G06F3/06 ,  G06F13/42

    Abstract: Techniques to facilitate an out-of-band (OOB) management in a virtualization environment include examples of assigning an endpoint identifier to a domain mapped to physical memory addresses of one or more storage devices coupled with a computing platform. The domain may enable software or a device driver executed by a virtual machine (VM) to access, manage or control at least a portion of the one or more storage devices. Examples also include receiving or forwarding messages through an OOB communication link coupled with the computing platform to a management entity to facilitate OOB management of the software or the device driver executed by the VM.

    SYSTEM RESOURCE ALLOCATION FOR CODE EXECUTION
    10.
    发明申请
    SYSTEM RESOURCE ALLOCATION FOR CODE EXECUTION 有权

    公开(公告)号：US20220058062A1

    公开(公告)日：2022-02-24

    申请号：US17520700

    申请日：2021-11-07

    Applicant: Intel Corporation

    Inventor： Rafal SZTEJNA ,  Piotr WYSOCKI ,  Pawel ZAK ,  Przemyslaw PERYCZ ,  Szymon KONEFAL

    IPC: G06F9/50 ,  G06F9/54

    Abstract: Examples described herein relate to an including at least one processor and a system agent communicatively coupled to the at least one processor. In some examples, the at least one of the at least one processor, when operational, is configured to: execute an operating system (OS) to: receive a call to perform a kernel-level operation and adjust settings of system resources assigned to perform the kernel-level operation based on a class of service associated with the call.

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