公开(公告)号：US09535744B2

公开(公告)日：2017-01-03

申请号：US13931860

申请日：2013-06-29

Applicant: Intel Corporation

Inventor： Ravi Rajwar ,  Matthew C. Merten ,  Christine E. Wang ,  Vijaykumar B. Kadgi ,  Rajesh S. Parthasarathy

IPC: G06F9/46 ,  G06F9/38 ,  G06F9/52

CPC classification number: G06F9/467 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3842 ,  G06F9/3857 ,  G06F9/3861 ,  G06F9/3863 ,  G06F9/466 ,  G06F9/528

Abstract: A processor, system, and method are described for continued retirement of operations during a commit of a speculative region of program code. For example, one embodiment of a method comprises the operations of identifying a plurality of transactional memory regions in program code, including a first transactional memory region; and retiring one or more of a plurality of operations which follow the first transactional memory region even when a commit operation associated with the first transactional memory region is waiting to complete.

Abstract translation: 描述了处理器，系统和方法，用于在提交程序代码的推测区域期间继续退出操作。 例如，方法的一个实施例包括在程序代码中识别多个事务存储区域的操作，包括第一事务存储器区域; 以及即使当与第一事务存储器区域相关联的提交操作等待完成时，退出遵循第一事务存储器区域的多个操作中的一个或多个操作。

公开(公告)号：US09465647B2

公开(公告)日：2016-10-11

申请号：US14048451

申请日：2013-10-08

Applicant: INTEL CORPORATION

Inventor： Mahesh Natu ,  Thanunathan Rangarajan ,  Gautam Doshi ,  Shamanna M. Datta ,  Baskaran Ganesan ,  Mohan J. Kumar ,  Rajesh S. Parthasarathy ,  Frank Binns ,  Rajesh Nagaraja Murthy ,  Robert C. Swanson

IPC: G06F9/48 ,  G06F9/46 ,  G06F9/30 ,  G06F9/38

CPC classification number: G06F13/24 ,  G06F9/30101 ,  G06F9/3017 ,  G06F9/30189 ,  G06F9/3851 ,  G06F9/461 ,  G11C7/1072 ,  G11C11/40615

Abstract: In one embodiment, the present invention includes a processor that has an on-die storage such as a static random access memory to store an architectural state of one or more threads that are swapped out of architectural state storage of the processor on entry to a system management mode (SMM). In this way communication of this state information to a system management memory can be avoided, reducing latency associated with entry into SMM. Embodiments may also enable the processor to update a status of executing agents that are either in a long instruction flow or in a system management interrupt (SMI) blocked state, in order to provide an indication to agents inside the SMM. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括具有诸如静态随机存取存储器之类的片上存储器的处理器，用于存储在进入系统时从处理器的架构状态存储器交换的一个或多个线程的架构状态 管理模式（SMM）。 以这种方式，可以避免该状态信息与系统管理存储器的通信，减少与进入SMM相关联的延迟。 实施例还可以使处理器更新处于长指令流或处于系统管理中断（SMI）阻塞状态中的执行代理的状态，以向SMM内的代理提供指示。 描述和要求保护其他实施例。