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    Providing State Storage in a Processor for System Management Mode
    1.
    发明申请
    Providing State Storage in a Processor for System Management Mode 审中-公开
    在处理器中为系统管理模式提供状态存储

    公开(公告)号：US20170010991A1

    公开(公告)日：2017-01-12

    申请号：US15270151

    申请日：2016-09-20

    Applicant: Intel Corporation

    Inventor： Mahesh Natu ,  Thanunathan Rangarajan ,  Gautam Doshi ,  Shamanna M. Datta ,  Baskaran Ganesan ,  Mohan J. Kumar ,  Rajesh S. Parthasarathy ,  Frank Binns ,  Rajesh Nagaraja Murthy ,  Robert C. Swanson

    IPC: G06F13/24 ,  G11C7/10 ,  G11C11/406

    CPC classification number: G06F13/24 ,  G06F9/30101 ,  G06F9/3017 ,  G06F9/30189 ,  G06F9/3851 ,  G06F9/461 ,  G11C7/1072 ,  G11C11/40615

    Abstract: In one embodiment, the present invention includes a processor that has an on-die storage such as a static random access memory to store an architectural state of one or more threads that are swapped out of architectural state storage of the processor on entry to a system management mode (SMM). In this way communication of this state information to a system management memory can be avoided, reducing latency associated with entry into SMM. Embodiments may also enable the processor to update a status of executing agents that are either in a long instruction flow or in a system management interrupt (SMI) blocked state, in order to provide an indication to agents inside the SMM. Other embodiments are described and claimed.

    Abstract translation: 在一个实施例中，本发明包括具有诸如静态随机存取存储器之类的片上存储器的处理器，用于存储在进入系统时从处理器的体系结构状态存储器交换的一个或多个线程的架构状态 管理模式（SMM）。 以这种方式，可以避免该状态信息与系统管理存储器的通信，减少与进入SMM相关联的延迟。 实施例还可以使处理器更新处于长指令流或处于系统管理中断（SMI）阻塞状态中的执行代理的状态，以向SMM内的代理提供指示。 描述和要求保护其他实施例。

    SYSTEMS AND METHODS TO REJUVENATE NONVOLATILE MEMORY USING TIMESTAMPS
    3.
    发明申请
    SYSTEMS AND METHODS TO REJUVENATE NONVOLATILE MEMORY USING TIMESTAMPS 审中-公开
    使用时间戳记重新获取非易失性存储器的系统和方法

    公开(公告)号：US20170062023A1

    公开(公告)日：2017-03-02

    申请号：US14836923

    申请日：2015-08-26

    Applicant: Intel Corporation

    Inventor： Shamanna M. Datta ,  Richard P. Mangold ,  Mahesh S. Natu

    IPC: G11C5/14

    CPC classification number: G11C5/148 ,  G06F2212/72 ,  G06F2212/7209 ,  G11C16/3418 ,  G11C16/349 ,  G11C29/4401 ,  G11C29/70

    Abstract: Apparatus, systems, and methods to implement boot operations in nonvolatile storage devices can include, in one example, a controller comprising logic to receive a power down instruction, record a timestamp associated with the power down instruction, and store the timestamp in a nonvolatile memory table communicatively coupled to the controller. Other examples are also disclosed and claimed.

    Abstract translation: 在一个示例中，可以包括用于实现非易失性存储设备中的引导操作的装置，系统和方法，所述控制器包括用于接收掉电指令，记录与掉电指令相关联的时间戳并将所述时间戳存储在非易失性存储器 表通信耦合到控制器。 还公开并要求保护其他实例。

    SECURE TUNNELING ACCESS TO DEBUG TEST PORTS ON NON-VOLATILE MEMORY STORAGE UNITS
    5.
    发明申请
    SECURE TUNNELING ACCESS TO DEBUG TEST PORTS ON NON-VOLATILE MEMORY STORAGE UNITS 审中-公开

    公开(公告)号：US20180067794A1

    公开(公告)日：2018-03-08

    申请号：US15707475

    申请日：2017-09-18

    Applicant: Intel Corporation

    Inventor： Shamanna M. Datta ,  Murugasamy K. Nachimuthu ,  Mahesh S. Natu

    IPC: G06F11/07 ,  G06F12/14 ,  G06F11/263 ,  G06F11/22 ,  G06F11/16

    Abstract: Systems, apparatuses and methods may provide for receiving one or more debug communications and programming, via a bus, a set of debug registers with debug information corresponding to the one or more debug communications. Additionally, tunnel logic hardware may be instructed to transfer the debug information from the set of debug registers to one or more test access ports of an intelligent device such as a non-volatile memory storage unit having a microcontroller. In one example, if it is detected that debug permission has been granted during a boot process, a control status register may be unlocked. If, on the other hand, the debug permission is not detected during the boot process, the control status register may be locked. Accordingly, an enable bit of the control status register may be used to activate the tunnel logic hardware only if the control status register is unlocked.

    Runtime firmware activation for memory devices
    7.
    发明授权
    Runtime firmware activation for memory devices 有权

    公开(公告)号：US11379214B2

    公开(公告)日：2022-07-05

    申请号：US16369161

    申请日：2019-03-29

    Applicant: Intel Corporation

    Inventor： Murugasamy K. Nachimuthu ,  Mohan J. Kumar ,  Shamanna M. Datta

    IPC: G06F9/44 ,  G06F8/656 ,  G06F8/654 ,  G06F3/06 ,  G06F9/4401

    Abstract: An interface is provided to update a firmware of a persistent memory module at runtime without restarting an operating system on the platform. The operating system initiates the firmware update by triggering a sleep state or by entering a soft reboot. The interface is capable of preserving the state of the platform for all memory modes that support volatile memory regions, persistent memory regions, or both, and reducing or eliminating the demand for access to memory during the firmware update. The persistent memory module is capable of updating the firmware responsive to a platform instruction generated using the interface, including preserving operational states for memory devices in all memory regions, including memory devices in volatile and persistent memory regions.

    Layered virtual machine integrity monitoring
    9.
    发明授权
    Layered virtual machine integrity monitoring 有权

    公开(公告)号：US09720716B2

    公开(公告)日：2017-08-01

    申请号：US13797924

    申请日：2013-03-12

    Applicant: Intel Corporation

    Inventor： Mahesh S. Natu ,  Shamanna M. Datta

    IPC: G06F9/455 ,  G06F11/30 ,  G06F21/53 ,  G06F21/57

    CPC classification number: G06F9/45533 ,  G06F9/45558 ,  G06F11/30 ,  G06F21/53 ,  G06F21/57 ,  G06F2009/45591

    Abstract: Various embodiments are generally directed to the provision and use of various hardware and software components of a computing device to monitor the state of layered virtual machine (VM) monitoring software components. An apparatus includes a first processor element; and logic to receive an indication that a first timer has reached an end of a first period of time, monitor execution of a VMM (virtual machine monitor) watcher by a second processor element, determine whether the second processor element completes execution of the VMM watcher to verify integrity of a VMM before a second timer reaches an end of a second period of time, and transmit an indication of the determination to a computing device. Other embodiments are described and claimed.

    Secure tunneling access to debug test ports on non-volatile memory storage units
    10.
    发明授权
    Secure tunneling access to debug test ports on non-volatile memory storage units 审中-公开

    公开(公告)号：US10671466B2

    公开(公告)日：2020-06-02

    申请号：US15707475

    申请日：2017-09-18

    Applicant: Intel Corporation

    Inventor： Shamanna M. Datta ,  Murugasamy K. Nachimuthu ,  Mahesh S. Natu

    IPC: G06F11/07 ,  G06F11/263 ,  G06F11/22 ,  G06F11/16 ,  G06F12/14 ,  G06F11/36

    Abstract: Systems, apparatuses and methods may provide for receiving one or more debug communications and programming, via a bus, a set of debug registers with debug information corresponding to the one or more debug communications. Additionally, tunnel logic hardware may be instructed to transfer the debug information from the set of debug registers to one or more test access ports of an intelligent device such as a non-volatile memory storage unit having a microcontroller. In one example, if it is detected that debug permission has been granted during a boot process, a control status register may be unlocked. If, on the other hand, the debug permission is not detected during the boot process, the control status register may be locked. Accordingly, an enable bit of the control status register may be used to activate the tunnel logic hardware only if the control status register is unlocked.

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