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    Length determination of instruction code with address form field and escape opcode value by evaluating portions other than instruction specific opcode
    1.
    发明授权
    Length determination of instruction code with address form field and escape opcode value by evaluating portions other than instruction specific opcode 有权
    通过评估除指令特定操作码之外的部分，具有地址表单字段和转义操作码值的指令代码的长度确定

    公开(公告)号：US08793470B2

    公开(公告)日：2014-07-29

    申请号：US13844471

    申请日：2013-03-15

    Applicant: Intel Corporation

    Inventor： James S. Coke ,  Peter J. Ruscito ,  Masood Tahir ,  David B. Jackson ,  Ves A. Naydenov ,  Scott D. Rodgers ,  Bret L. Toll ,  Frank Binns

    IPC: G06F9/30

    CPC classification number: G06F9/30149 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30185

    Abstract: A method, apparatus and system are disclosed for decoding an instruction in a variable-length instruction set. The instruction is one of a set of new types of instructions that uses a new escape code value, which is two bytes in length, to indicate that a third opcode byte includes the instruction-specific opcode for a new instruction. The new instructions are defined such the length of each instruction in the opcode map for one of the new escape opcode values may be determined using the same set of inputs, where each of the inputs is relevant to determining the length of each instruction in the new opcode map. For at least one embodiment, the length of one of the new instructions is determined without evaluating the instruction-specific opcode.

    Abstract translation: 公开了用于对可变长度指令集中的指令进行解码的方法，装置和系统。 该指令是一组新的指令之一，它使用长度为两个字节的新的转义码值来指示第三个操作码字节包含新指令的指令特定操作码。 定义新指令，可以使用相同的一组输入来确定新的转义操作码值之一的操作码映射中每个指令的长度，其中每个输入与确定新指令中的每个指令的长度相关 操作码地图。 对于至少一个实施例，在不评估指令特定操作码的情况下确定新指令之一的长度。

    Minimizing bandwith to compress output stream in instruction tracing systems
    5.
    发明授权
    Minimizing bandwith to compress output stream in instruction tracing systems 有权

    公开(公告)号：US09753832B2

    公开(公告)日：2017-09-05

    申请号：US13930501

    申请日：2013-06-28

    Applicant: Intel Corporation

    Inventor： Ilya Wagner ,  Matthew C. Merten ,  Frank Binns ,  Christine E. Wang ,  Mayank Bomb ,  Tong Li ,  Thilo Schmitt ,  M D A. Rahman

    IPC: G06F9/30 ,  G06F11/34

    CPC classification number: G06F11/3466 ,  G06F11/348 ,  G06F2201/81

    Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for minimizing bandwidth to compress an output stream of an instruction tracing system. For example, the method may include identifying a current instruction in a trace of the IT module as a conditional branch (CB) instruction. The method includes executing one of generating a CB packet including a byte pattern with an indication of outcome of the CB instruction, or adding an indication of the outcome of the CB instruction to the byte pattern of an existing CB packet. The method includes generating a packet when a subsequent instruction in the trace is not the CB instruction. The packet is different from the CB packet. The method also includes adding the packet into a deferred queue when the packet is deferrable. The method further includes outputting the CB packet followed by the deferred packet into a packet log.

    Providing State Storage in a Processor for System Management Mode
    6.
    发明申请
    Providing State Storage in a Processor for System Management Mode 审中-公开
    在处理器中为系统管理模式提供状态存储

    公开(公告)号：US20170010991A1

    公开(公告)日：2017-01-12

    申请号：US15270151

    申请日：2016-09-20

    Applicant: Intel Corporation

    Inventor： Mahesh Natu ,  Thanunathan Rangarajan ,  Gautam Doshi ,  Shamanna M. Datta ,  Baskaran Ganesan ,  Mohan J. Kumar ,  Rajesh S. Parthasarathy ,  Frank Binns ,  Rajesh Nagaraja Murthy ,  Robert C. Swanson

    IPC: G06F13/24 ,  G11C7/10 ,  G11C11/406

    CPC classification number: G06F13/24 ,  G06F9/30101 ,  G06F9/3017 ,  G06F9/30189 ,  G06F9/3851 ,  G06F9/461 ,  G11C7/1072 ,  G11C11/40615

    Abstract: In one embodiment, the present invention includes a processor that has an on-die storage such as a static random access memory to store an architectural state of one or more threads that are swapped out of architectural state storage of the processor on entry to a system management mode (SMM). In this way communication of this state information to a system management memory can be avoided, reducing latency associated with entry into SMM. Embodiments may also enable the processor to update a status of executing agents that are either in a long instruction flow or in a system management interrupt (SMI) blocked state, in order to provide an indication to agents inside the SMM. Other embodiments are described and claimed.

    Abstract translation: 在一个实施例中，本发明包括具有诸如静态随机存取存储器之类的片上存储器的处理器，用于存储在进入系统时从处理器的体系结构状态存储器交换的一个或多个线程的架构状态 管理模式（SMM）。 以这种方式，可以避免该状态信息与系统管理存储器的通信，减少与进入SMM相关联的延迟。 实施例还可以使处理器更新处于长指令流或处于系统管理中断（SMI）阻塞状态中的执行代理的状态，以向SMM内的代理提供指示。 描述和要求保护其他实施例。

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