公开(公告)号：US20200219970A1

公开(公告)日：2020-07-09

申请号：US16240156

申请日：2019-01-04

Applicant: Intel Corporation

Inventor： Ehren Mannebach ,  Anh Phan ,  Aaron Lilak ,  Willy Rachmady ,  Gilbert Dewey ,  Cheng-Ying Huang ,  Richard Schenker ,  Hui Jae Yoo ,  Patrick Morrow

IPC: H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L27/088

Abstract: Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures using multiple bottom-up oxidation approaches, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires. All nanowires of the vertical arrangement of nanowires are oxide nanowires. A gate stack is over the vertical arrangement of nanowires, around each of the oxide nanowires. The gate stack includes a conductive gate electrode.

公开(公告)号：US20240071913A1

公开(公告)日：2024-02-29

申请号：US17894380

申请日：2022-08-24

Applicant: Intel Corporation

Inventor： June Choi ,  Richard Schenker ,  Charles H. Wallace ,  Nikhil J. Mehta ,  Clifford L. Ong

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L23/528 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/5329

Abstract: An integrated circuit structure includes a first interconnect layer, and a second interconnect layer above the first interconnect layer. The first interconnect layer includes a first interconnect feature and a second interconnect feature. The second interconnect layer includes a third interconnect feature, a fourth interconnect feature, and a fifth interconnection feature. The third interconnect feature extends from an upper surface of the first interconnect feature to an upper surface of the second interconnect layer. In an example, the fourth interconnect feature extends from an upper surface of the second interconnect feature to below the upper surface of the second interconnect layer, and the fifth interconnect feature extends from an upper surface of the fourth interconnect feature to the upper surface of the second interconnect layer. Thus, a double-decked vertical stack of interconnect features is formed using the fourth interconnect feature within the second interconnect layer.

公开(公告)号：US11569231B2

公开(公告)日：2023-01-31

申请号：US16354669

申请日：2019-03-15

Applicant: Intel Corporation

Inventor： Stephen D Snyder ,  Leonard Guler ,  Richard Schenker ,  Michael K Harper ,  Sam Sivakumar ,  Urusa Alaan ,  Stephanie A Bojarski ,  Achala Bhuwalka

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/10 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/16 ,  H01L29/20 ,  H01L21/02 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/8252 ,  H01L21/8238

Abstract: Techniques are disclosed for non-planar transistors having varying channel widths (Wsi). In some instances, the resulting structure has a fin (or nanowires, nanoribbons, or nanosheets) comprising a first channel region and a second channel region, with a source or drain region between the first channel region and the second channel region. The widths of the respective channel regions are independent of each other, e.g., a first width of the first channel region is different from a second width of the second channel region. The variation in width of a given fin structure may vary in a symmetric fashion or an asymmetric fashion. In an embodiment, a spacer-based forming approach is utilized that allows for abrupt changes in width along a given fin. Sub-resolution fin dimensions are achievable as well.

公开(公告)号：US11424160B2

公开(公告)日：2022-08-23

申请号：US16274758

申请日：2019-02-13

Applicant: INTEL CORPORATION

Inventor： Aaron D. Lilak ,  Ehren Mannebach ,  Anh Phan ,  Richard Schenker ,  Stephanie A. Bojarski ,  Willy Rachmady ,  Patrick Morrow ,  Jeffery Bielefeld ,  Gilbert Dewey ,  Hui Jae Yoo ,  Nafees Kabir

IPC: H01L21/768 ,  H01L29/78 ,  H01L29/66 ,  H01L27/092 ,  H01L23/522 ,  H01L21/8238 ,  H01L21/02

Abstract: In some embodiments, a semiconductor device structure is formed by using an angled etch to remove material so as to expose a portion of an adjacent conductor. The space formed upon removing the material can then be filled with a conductive material during formation of a contact or other conductive structure (e.g., and interconnection). In this way, the contact formation also fills the space to form an angled local interconnect portion that connects adjacent structures (e.g., a source/drain contact to an adjacent source/drain contact, a source/drain contact to an adjacent gate contact, a source/drain contact to an adjacent device level conductor also connected to a gate/source/drain contact). In other embodiments, an interconnection structure herein termed a “jogged via” establishes and electrical connection from laterally adjacent peripheral surfaces of conductive structures that are not coaxially or concentrically aligned with one another.

公开(公告)号：US20200295002A1

公开(公告)日：2020-09-17

申请号：US16354669

申请日：2019-03-15

Applicant: Intel Corporation

Inventor： Stephen D. Snyder ,  Leonard Guler ,  Richard Schenker ,  Michael K. Harper ,  Sam Sivakumar ,  Urusa Alaan ,  Stephanie A. Bojarski ,  Achala Bhuwalka

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/10 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/16 ,  H01L29/20 ,  H01L21/02 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/8252 ,  H01L21/8238

Abstract: Techniques are disclosed for non-planar transistors having varying channel widths (Wsi). In some instances, the resulting structure has a fin (or nanowires, nanoribbons, or nanosheets) comprising a first channel region and a second channel region, with a source or drain region between the first channel region and the second channel region. The widths of the respective channel regions are independent of each other, e.g., a first width of the first channel region is different from a second width of the second channel region. The variation in width of a given fin structure may vary in a symmetric fashion or an asymmetric fashion. In an embodiment, a spacer-based forming approach is utilized that allows for abrupt changes in width along a given fin. Sub-resolution fin dimensions are achievable as well.

公开(公告)号：US20200258778A1

公开(公告)日：2020-08-13

申请号：US16274758

申请日：2019-02-13

Applicant: INTEL CORPORATION

Inventor： Aaron D. Lilak ,  Ehren Mannebach ,  Anh Phan ,  Richard Schenker ,  Stephanie A. Bojarski ,  Willy Rachmady ,  Patrick Morrow ,  Jeffery Bielefeld ,  Gilbert Dewey ,  Hui Jae Yoo ,  Nafees Kabir

IPC: H01L21/768 ,  H01L29/78 ,  H01L29/66 ,  H01L27/092 ,  H01L23/522 ,  H01L21/02 ,  H01L21/8238

Abstract: In some embodiments, a semiconductor device structure is formed by using an angled etch to remove material so as to expose a portion of an adjacent conductor. The space formed upon removing the material can then be filled with a conductive material during formation of a contact or other conductive structure (e.g., and interconnection). In this way, the contact formation also fills the space to form an angled local interconnect portion that connects adjacent structures (e.g., a source/drain contact to an adjacent source/drain contact, a source/drain contact to an adjacent gate contact, a source/drain contact to an adjacent device level conductor also connected to a gate/source/drain contact). In other embodiments, an interconnection structure herein termed a “jogged via” establishes and electrical connection from laterally adjacent peripheral surfaces of conductive structures that are not coaxially or concentrically aligned with one another.