公开(公告)号：US12107085B2

公开(公告)日：2024-10-01

申请号：US18219374

申请日：2023-07-07

申请人： Intel Corporation

发明人： Aaron D. Lilak ,  Gilbert Dewey ,  Cheng-Ying Huang ,  Christopher Jezewski ,  Ehren Mannebach ,  Rishabh Mehandru ,  Patrick Morrow ,  Anand S. Murthy ,  Anh Phan ,  Willy Rachmady

IPC分类号： H01L27/088 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/8258 ,  H01L21/84 ,  H01L23/00 ,  H01L23/48 ,  H01L23/522 ,  H01L23/538 ,  H01L27/06 ,  H01L27/092

CPC分类号： H01L27/0886 ,  H01L21/76898 ,  H01L21/8258 ,  H01L21/845 ,  H01L23/481 ,  H01L23/5226 ,  H01L24/29 ,  H01L24/32 ,  H01L27/0924 ,  H01L24/94 ,  H01L2224/29188 ,  H01L2224/32145

摘要： Stacked transistor structures having a conductive interconnect between source/drain regions of upper and lower transistors. In some embodiments, the interconnect is provided, at least in part, by highly doped epitaxial material deposited in the upper transistor's source/drain region. In such cases, the epitaxial material seeds off of an exposed portion of semiconductor material of or adjacent to the upper transistor's channel region and extends downward into a recess that exposes the lower transistor's source/drain contact structure. The epitaxial source/drain material directly contacts the lower transistor's source/drain contact structure, to provide the interconnect. In other embodiments, the epitaxial material still seeds off the exposed semiconductor material of or proximate to the channel region and extends downward into the recess, but need not contact the lower contact structure. Rather, a metal-containing contact structure passes through the epitaxial material of the upper source/drain region and contacts the lower transistor's source/drain contact structure.

公开(公告)号：US11996411B2

公开(公告)日：2024-05-28

申请号：US16913796

申请日：2020-06-26

申请人： Intel Corporation

发明人： Cheng-Ying Huang ,  Gilbert Dewey ,  Anh Phan ,  Nicole K. Thomas ,  Urusa Alaan ,  Seung Hoon Sung ,  Christopher M. Neumann ,  Willy Rachmady ,  Patrick Morrow ,  Hui Jae Yoo ,  Richard E. Schenker ,  Marko Radosavljevic ,  Jack T. Kavalieros ,  Ehren Mannebach

IPC分类号： H01L29/78 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H10B12/00

CPC分类号： H01L27/0924 ,  H01L29/0673 ,  H01L29/4232 ,  H01L29/775 ,  H01L29/7851 ,  H10B12/056

摘要： Embodiments disclosed herein include stacked forksheet transistor devices, and methods of fabricating stacked forksheet transistor devices. In an example, an integrated circuit structure includes a backbone. A first transistor device includes a first vertical stack of semiconductor channels adjacent to an edge of the backbone. A second transistor device includes a second vertical stack of semiconductor channels adjacent to the edge of the backbone. The second transistor device is stacked on the first transistor device.

公开(公告)号：US11830933B2

公开(公告)日：2023-11-28

申请号：US16240369

申请日：2019-01-04

申请人： Intel Corporation

发明人： Willy Rachmady ,  Gilbert Dewey ,  Jack T. Kavalieros ,  Aaron Lilak ,  Patrick Morrow ,  Anh Phan ,  Cheng-Ying Huang ,  Ehren Mannebach

IPC分类号： H01L29/00 ,  H01L29/66 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

CPC分类号： H01L29/66742 ,  H01L21/02236 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823892 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/78696

摘要： Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures using a bottom-up oxidation approach, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires above a substrate. The vertical arrangement of nanowires has one or more active nanowires above one or more oxidized nanowires. A gate stack is over the vertical arrangement of nanowires and around the one or more oxidized nanowires.

公开(公告)号：US20230145229A1

公开(公告)日：2023-05-11

申请号：US17522342

申请日：2021-11-09

申请人： Intel Corporation

发明人： Nicole K. Thomas ,  Ashish Agrawal ,  Gilbert Dewey ,  Cheng-Ying Huang ,  Ehren Mannebach ,  Willy Rachmady ,  Marko Radosavljevic

IPC分类号： H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L27/088

CPC分类号： H01L29/42392 ,  H01L29/0665 ,  H01L29/78696 ,  H01L27/088

摘要： Techniques are provided herein to form semiconductor devices having backside contacts. Sacrificial plugs are formed first within a substrate at particular locations to align with source and drain regions during a later stage of processing. Another wafer is subsequently bonded to the surface of the substrate and is thinned to effectively transfer different material layers to the top surface of the substrate. One of the transferred layers acts as a seed layer for the growth of additional semiconductor material used to form semiconductor devices. The source and drain regions of the semiconductor devices are sufficiently aligned over the previously formed sacrificial plugs. A backside portion of the substrate may be removed to expose the sacrificial plugs from the backside. Removal of the plugs and replacement of the recesses left behind with conductive material forms the conductive backside contacts to the source or drain regions.

公开(公告)号：US11573798B2

公开(公告)日：2023-02-07

申请号：US16290544

申请日：2019-03-01

申请人： Intel Corporation

发明人： Aaron D. Lilak ,  Gilbert W. Dewey ,  Willy Rachmady ,  Rishabh Mehandru ,  Ehren Mannebach ,  Cheng-Ying Huang ,  Anh Phan ,  Patrick Morrow

IPC分类号： H01L29/772 ,  G06F9/30 ,  G06F9/34 ,  H01L29/78 ,  H01L29/66 ,  H01L29/786 ,  H01L29/775

摘要： Disclosed herein are stacked transistors with different gate lengths in different device strata, as well as related methods and devices. In some embodiments, an integrated circuit structure may include stacked strata of transistors, with two different device strata having different gate lengths.

公开(公告)号：US11437283B2

公开(公告)日：2022-09-06

申请号：US16355195

申请日：2019-03-15

申请人： INTEL CORPORATION

发明人： Aaron D. Lilak ,  Ehren Mannebach ,  Anh Phan ,  Richard E. Schenker ,  Stephanie A. Bojarski ,  Willy Rachmady ,  Patrick R. Morrow ,  Jeffery D. Bielefeld ,  Gilbert Dewey ,  Hui Jae Yoo

IPC分类号： H01L21/8234 ,  H01L27/088 ,  H01L29/78 ,  H01L29/06 ,  H01L23/532 ,  H01L23/48

摘要： Backside contact structures include etch selective materials to facilitate backside contact formation. An integrated circuit structure includes a frontside contact region, a device region below the frontside contact region, and a backside contact region below the device region. The device region includes a transistor. The backside contact region includes a first dielectric material under a source or drain region of the transistor, a second dielectric material laterally adjacent to the first dielectric material and under a gate structure of the transistor. A non-conductive spacer is between the first and second dielectric materials. The first and second dielectric materials are selectively etchable with respect to one another and the spacer. The backside contact region may include an interconnect feature that, for instance, passes through the first dielectric material and contacts a bottom side of the source/drain region, and/or passes through the second dielectric material and contacts the gate structure.

公开(公告)号：US11348916B2

公开(公告)日：2022-05-31

申请号：US16024076

申请日：2018-06-29

申请人： INTEL CORPORATION

发明人： Aaron D. Lilak ,  Anh Phan ,  Ehren Mannebach ,  Cheng-Ying Huang ,  Stephanie A. Bojarski ,  Gilbert Dewey ,  Orb Acton ,  Willy Rachmady

IPC分类号： H01L27/088 ,  H01L29/423 ,  H01L29/08 ,  H01L21/762 ,  H01L23/528 ,  H01L29/78 ,  H01L29/06

摘要： Stacked transistor structures having a conductive interconnect between upper and lower transistors. In an embodiment, the interconnect is formed by first provisioning a protective layer over an area to be protected (gate dielectric or other sensitive material) of upper transistor, and then etching material adjacent and below the protected area to expose an underlying contact point of lower transistor. A metal is deposited into the void created by the etch to provide the interconnect. The protective layer is resistant to the etch process and is preserved in the structure, and in some cases may be utilized as a work-function metal. In an embodiment, the protective layer is formed by deposition of reactive semiconductor and metal material layers which are subsequently transformed into a work function metal or work function metal-containing compound. A remnant of unreacted reactive semiconductor material may be left in structure and collinear with protective layer.

公开(公告)号：US20200295127A1

公开(公告)日：2020-09-17

申请号：US16351921

申请日：2019-03-13

申请人： Intel Corporation

发明人： Ehren Mannebach ,  Aaron D. Lilak ,  Anh Phan ,  Cheng-Ying Huang ,  Gilbert W. Dewey ,  Patrick Morrow ,  Rishabh Mehandru ,  Roza Kotlyar ,  Sean T. Ma ,  Willy Rachmady

IPC分类号： H01L29/04 ,  H01L29/78 ,  H01L29/06 ,  H01L27/092 ,  H01L25/11 ,  H01L23/00 ,  H01L23/522 ,  H01L29/16 ,  H01L29/20 ,  H01L21/8238 ,  H01L29/66

摘要： Disclosed herein are stacked transistors with different crystal orientations in different device strata, as well as related methods and devices. In some embodiments, an integrated circuit structure may include stacked strata of transistors, wherein the channel materials in at least some of the strata have different crystal orientations.

公开(公告)号：US11916118B2

公开(公告)日：2024-02-27

申请号：US18130824

申请日：2023-04-04

申请人： Intel Corporation

发明人： Ehren Mannebach ,  Aaron Lilak ,  Hui Jae Yoo ,  Patrick Morrow ,  Anh Phan ,  Willy Rachmady ,  Cheng-Ying Huang ,  Gilbert Dewey

IPC分类号： H01L29/417

CPC分类号： H01L29/41741 ,  H01L29/41775

摘要： A device is disclosed. The device includes a first epitaxial region, a second epitaxial region, a first gate region between the first epitaxial region and a second epitaxial region, a first dielectric structure underneath the first epitaxial region, a second dielectric structure underneath the second epitaxial region, a third epitaxial region underneath the first epitaxial region, a fourth epitaxial region underneath the second epitaxial region, and a second gate region between the third epitaxial region and a fourth epitaxial region and below the first gate region. The device also includes, a conductor via extending from the first epitaxial region, through the first dielectric structure and the third epitaxial region, the conductor via narrower at an end of the conductor via that contacts the first epitaxial region than at an opposite end.

公开(公告)号：US11764263B2

公开(公告)日：2023-09-19

申请号：US16240156

申请日：2019-01-04

申请人： Intel Corporation

发明人： Ehren Mannebach ,  Anh Phan ,  Aaron Lilak ,  Willy Rachmady ,  Gilbert Dewey ,  Cheng-Ying Huang ,  Richard Schenker ,  Hui Jae Yoo ,  Patrick Morrow

IPC分类号： H01L29/06 ,  H01L27/088 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423

CPC分类号： H01L29/068 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858

摘要： Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures using multiple bottom-up oxidation approaches, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires. All nanowires of the vertical arrangement of nanowires are oxide nanowires. A gate stack is over the vertical arrangement of nanowires, around each of the oxide nanowires. The gate stack includes a conductive gate electrode.