公开(公告)号：US12068314B2

公开(公告)日：2024-08-20

申请号：US17026047

申请日：2020-09-18

Applicant: Intel Corporation

Inventor： Leonard P. Guler ,  William Hsu ,  Biswajeet Guha ,  Martin Weiss ,  Apratim Dhar ,  William T. Blanton ,  John H. Irby, IV ,  James F. Bondi ,  Michael K. Harper ,  Charles H. Wallace ,  Tahir Ghani ,  Benedict A. Samuel ,  Stefan Dickert

IPC: H01L27/088 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L27/0886 ,  H01L29/42392 ,  H01L29/7851 ,  H01L29/78696

Abstract: Gate-all-around integrated circuit structures having adjacent island structures are described. For example, an integrated circuit structure includes a semiconductor island on a semiconductor substrate. A first vertical arrangement of horizontal nanowires is above a first fin protruding from the semiconductor substrate. A channel region of the first vertical arrangement of horizontal nanowires is electrically isolated from the fin. A second vertical arrangement of horizontal nanowires is above a second fin protruding from the semiconductor substrate. A channel region of the second vertical arrangement of horizontal nanowires is electrically isolated from the second fin. The semiconductor island is between the first vertical arrangement of horizontal nanowires and the second vertical arrangement of horizontal nanowires.

公开(公告)号：US11594637B2

公开(公告)日：2023-02-28

申请号：US16833208

申请日：2020-03-27

Applicant: Intel Corporation

Inventor： Leonard P. Guler ,  Stephen Snyder ,  Biswajeet Guha ,  William Hsu ,  Urusa Alaan ,  Tahir Ghani ,  Michael K. Harper ,  Vivek Thirtha ,  Shu Zhou ,  Nitesh Kumar

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/786 ,  H01L29/165 ,  H01L21/02 ,  H01L29/10

Abstract: Gate-all-around integrated circuit structures having fin stack isolation, and methods of fabricating gate-all-around integrated circuit structures having fin stack isolation, are described. For example, an integrated circuit structure includes a sub-fin structure on a substrate, the sub-fin structure having a top and sidewalls. An isolation structure is on the top and along the sidewalls of the sub-fin structure. The isolation structure includes a first dielectric material surrounding regions of a second dielectric material. A vertical arrangement of horizontal nanowires is on a portion of the isolation structure on the top surface of the sub-fin structure.

公开(公告)号：US20200295002A1

公开(公告)日：2020-09-17

申请号：US16354669

申请日：2019-03-15

Applicant: Intel Corporation

Inventor： Stephen D. Snyder ,  Leonard Guler ,  Richard Schenker ,  Michael K. Harper ,  Sam Sivakumar ,  Urusa Alaan ,  Stephanie A. Bojarski ,  Achala Bhuwalka

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/10 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/16 ,  H01L29/20 ,  H01L21/02 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/8252 ,  H01L21/8238

Abstract: Techniques are disclosed for non-planar transistors having varying channel widths (Wsi). In some instances, the resulting structure has a fin (or nanowires, nanoribbons, or nanosheets) comprising a first channel region and a second channel region, with a source or drain region between the first channel region and the second channel region. The widths of the respective channel regions are independent of each other, e.g., a first width of the first channel region is different from a second width of the second channel region. The variation in width of a given fin structure may vary in a symmetric fashion or an asymmetric fashion. In an embodiment, a spacer-based forming approach is utilized that allows for abrupt changes in width along a given fin. Sub-resolution fin dimensions are achievable as well.

公开(公告)号：US11990472B2

公开(公告)日：2024-05-21

申请号：US17030212

申请日：2020-09-23

Applicant: Intel Corporation

Inventor： Leonard P. Guler ,  Michael K. Harper ,  William Hsu ,  Biswajeet Guha ,  Tahir Ghani ,  Niels Zussblatt ,  Jeffrey Miles Tan ,  Benjamin Kriegel ,  Mohit K. Haran ,  Reken Patel ,  Oleg Golonzka ,  Mohammad Hasan

IPC: H01L27/088 ,  G11C5/06 ,  H01L27/06 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0886 ,  G11C5/06 ,  H01L27/0688 ,  H01L29/0669 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858

Abstract: Gate-all-around integrated circuit structures having pre-spacer-deposition cut gates are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, and a second gate stack is over the second vertical arrangement of horizontal nanowires. An end of the second gate stack is spaced apart from an end of the first gate stack by a gap. The integrated circuit structure also includes a dielectric structure having a first portion forming a gate spacer along sidewalls of the first gate stack, a second portion forming a gate spacer along sidewalls of the second gate stack, and a third portion completely filling the gap, the third portion continuous with the first and second portions.

公开(公告)号：US12046652B2

公开(公告)日：2024-07-23

申请号：US16911705

申请日：2020-06-25

Applicant: Intel Corporation

Inventor： Nicole Thomas ,  Michael K. Harper ,  Leonard P. Guler ,  Marko Radosavljevic ,  Thoe Michaelos

IPC: H01L29/423 ,  H01L21/02 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/06

CPC classification number: H01L29/42392 ,  H01L21/0228 ,  H01L21/76897 ,  H01L21/823412 ,  H01L29/0669

Abstract: Embodiments disclosed herein include semiconductor devices and methods of making such devices. In an embodiment, the semiconductor device comprises a plurality of stacked semiconductor channels comprising first semiconductor channels and second semiconductor channels over the first semiconductor channels. In an embodiment a spacing is between the first semiconductor channels and the second semiconductor channels. The semiconductor device further comprises a gate dielectric surrounding individual ones of the semiconductor channels of the plurality of stacked semiconductor channels. In an embodiment, a first workfunction metal surrounds the first semiconductor channels, and a second workfunction metal surrounds the second semiconductor channels.

公开(公告)号：US09905693B2

公开(公告)日：2018-02-27

申请号：US15654597

申请日：2017-07-19

Applicant: Intel Corporation

Inventor： Michael L. Hattendorf ,  Pragyansri Pathi ,  Michael K. Harper

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L27/11

CPC classification number: H01L29/0653 ,  H01L27/1104 ,  H01L28/00 ,  H01L29/42376 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: Techniques related to integrated circuits having MOSFETs with an unrecessed field insulator and thinner electrodes over the field insulator of ICs, systems incorporating such integrated circuits, and methods for forming them are discussed.

公开(公告)号：US09768249B2

公开(公告)日：2017-09-19

申请号：US14778063

申请日：2013-06-26

Applicant: Intel Corporation

Inventor： Michael L. Hattendorf ,  Pragyansri Pathi ,  Michael K. Harper

IPC: H01L29/06 ,  H01L29/78 ,  H01L27/11 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/0653 ,  H01L27/1104 ,  H01L28/00 ,  H01L29/42376 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: Techniques related to integrated circuits having MOSFETs with an unrecessed field insulator and thinner electrodes over the field insulator of ICs, systems incorporating such integrated circuits, and methods for forming them are discussed.