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    VERTICALLY SPACED INTRA-LEVEL INTERCONNECT LINE METALLIZATION FOR INTEGRATED CIRCUIT DEVICES
    2.
    发明申请
    VERTICALLY SPACED INTRA-LEVEL INTERCONNECT LINE METALLIZATION FOR INTEGRATED CIRCUIT DEVICES 有权

    公开(公告)号：US20210407895A1

    公开(公告)日：2021-12-30

    申请号：US16914132

    申请日：2020-06-26

    申请人： Intel Corporation

    发明人： Kevin L. Lin ,  Sukru Yemenicioglu ,  Patrick Morrow ,  Richard Schenker ,  Mauro Kobrinsky

    IPC分类号： H01L23/498 ,  H01L21/768 ,  H05K1/11 ,  H05K3/00 ,  H05K3/40 ,  H01L27/088

    摘要： An integrated circuit interconnect level including a lower metallization line vertically spaced from upper metallization lines. Lower metallization lines may be self-aligned to upper metallization lines enabling increased metallization line width without sacrificing line density for a given interconnect level. Combinations of upper and lower metallization lines within an interconnect metallization level may be designed to control intra-layer resistance/capacitance of integrated circuit interconnect. Dielectric material between two adjacent co-planar metallization lines may be recessed or deposited selectively to the metallization lines. Supplemental metallization may then be deposited and planarized. A top surface of the supplemental metallization may either be recessed to form lower metallization lines between upper metallization lines, or planarized with dielectric material to form upper metallization lines between lower metallization lines. Vias to upper and lower metallization line may extend another metallization level.

    Single mask lithography line end enhancement
    8.
    发明授权
    Single mask lithography line end enhancement 有权

    公开(公告)号：US11462469B2

    公开(公告)日：2022-10-04

    申请号：US16143700

    申请日：2018-09-27

    申请人： INTEL CORPORATION

    发明人： Kevin L. Lin ,  Nafees A. Kabir ,  Richard Schenker

    IPC分类号： H01L23/522 ,  H01L21/768 ,  H01L23/532

    摘要： Techniques are disclosed that enable independent control of interconnect lines and line end structures using a single mask. The techniques provided are particularly useful, for instance, where single mask lithography processes limit the scaling of line end structures. In some embodiments, the techniques can be implemented using a liner body and multiple angled etches of the liner body to provide a line end structure comprised of a remaining portion of the liner body. In such cases, the line end structure material enables an etch rate that is slower than the etch rate of surrounding insulator materials. Furthermore, the line end structure can be of minimal size not attainable using conventional single mask processes. In other embodiments, the techniques can be implemented using a hardmask that includes hardmask features defining lines, and one or more angled etches of the hardmask to provide line end structure(s) of minimal size.

    Interconnects having a portion without a liner material and related structures, devices, and methods
    9.
    发明授权
    Interconnects having a portion without a liner material and related structures, devices, and methods 有权

    公开(公告)号：US11264325B2

    公开(公告)日：2022-03-01

    申请号：US16628991

    申请日：2017-09-28

    申请人： INTEL CORPORATION

    发明人： Manish Chandhok ,  Richard Schenker ,  Tristan Tronic

    IPC分类号： H01L23/528 ,  H01L21/768 ,  H01L23/532

    摘要： Integrated circuit (IC) structures, computing devices, and related methods are disclosed. An IC structure includes an interlayer dielectric (ILD), an interconnect, and a liner material separating the interconnect from the ILD. The interconnect includes a first end extending to or into the ILD and a second end opposite the first end. A second portion of the interconnect extending from the second end to a first portion of the interconnect proximate to the first end does not include the liner material thereon. A method of manufacturing an IC structure includes removing an ILD from between interconnects, applying a conformal hermetic liner, applying a carbon hard mask (CHM) between the interconnects, removing a portion of the CHM, removing the conformal hermetic liner to a remaining CHM, and removing the exposed portion of the liner material to the remaining CHM to expose the second portion of the interconnects.