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公开(公告)号：US12137169B2
公开(公告)日：2024-11-05
申请号：US17854911
申请日：2022-06-30
Applicant: Intel Corporation
Inventor： Santosh Ghosh , Vikram Suresh , Sanu Mathew , Manoj Sastry , Andrew H. Reinders , Raghavan Kumar , Rafael Misoczki
Abstract: In one example an apparatus comprises a computer readable memory, an XMSS verification manager logic to manage XMSS verification functions, a one-time signature and public key generator logic, a chain function logic to implement chain function algorithms, a low latency SHA3 hardware engine, and a register bank communicatively coupled to the XMSS verification manager logic. Other examples may be described.
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公开(公告)号：US12047485B2
公开(公告)日：2024-07-23
申请号：US17132365
申请日：2020-12-23
Applicant: Intel Corporation
Inventor： Raghavan Kumar , Xiaosen Liu , Harish Krishnamurthy , Sanu Mathew , Vikram Suresh
CPC classification number: H04L9/003 , G06F1/26 , H04L9/0631 , H04L2209/08
Abstract: Apparatus and method for resisting side-channel attacks on cryptographic engines are described herein. An apparatus embodiment includes a cryptographic block coupled to a non-linear low-dropout voltage regulator (NL-LDO). The NL-LDO includes a scalable power train to provide a variable load current to the cryptographic block, randomization circuitry to generate randomized values for setting a plurality of parameters, and a controller to adjust the variable load current provided to the cryptographic block based on the parameters and the current voltage of the cryptographic block. The controller to cause a decrease in the variable load current when the current voltage is above a high voltage threshold, an increase in the variable load current when the current voltage is below a low voltage threshold; and a maximization of the variable load current when the current voltage is below an undervoltage threshold. The cryptographic block may be implemented with arithmetic transformations.
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公开(公告)号：US11768966B2
公开(公告)日：2023-09-26
申请号：US17930326
申请日：2022-09-07
Applicant: Intel Corporation
Inventor： Vikram Suresh , Raghavan Kumar , Sanu Mathew
CPC classification number: G06F21/75 , G06F21/31 , G06F21/79 , G06F2221/2103
Abstract: A method comprises generating, during an enrollment process conducted in a controlled environment, a dark bit mask comprising a plurality of state information values derived from a plurality of entropy sources at a plurality of operating conditions for an electronic device, and using at least a portion of the plurality of state information values to generate a set of challenge-response pairs for use in an authentication process for the electronic device.
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14.发明授权公开(公告)号：US11456877B2
公开(公告)日：2022-09-27
申请号：US16456187
申请日：2019-06-28
Applicant: Intel Corporation
Inventor： Sanu Mathew , Manoj Sastry , Santosh Ghosh , Vikram Suresh , Andrew H. Reinders , Raghavan Kumar , Rafael Misoczki
Abstract: A mechanism is described for facilitating unified accelerator for classical and post-quantum digital signature schemes in computing environments. A method includes unifying classical cryptography and post-quantum cryptography through a unified hardware accelerator hosted by a trusted platform of the computing device. The method may further include facilitating unification of a first finite state machine associated with the classical cryptography and a second finite state machine associated with the post-quantum cryptography though one or more of a single the hash engine, a set of register file banks, and a modular exponentiation engine.
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公开(公告)号：US20220200784A1
公开(公告)日：2022-06-23
申请号：US17132365
申请日：2020-12-23
Applicant: Intel Corporation
Inventor： Raghavan Kumar , Xiaosen Liu , Harish Krishnamurthy , Sanu Mathew , Vikram Suresh
Abstract: Apparatus and method for resisting side-channel attacks on cryptographic engines are described herein. An apparatus embodiment includes a cryptographic block coupled to a non-linear low-dropout voltage regulator (NL-LDO). The NL-LDO includes a scalable power train to provide a variable load current to the cryptographic block, randomization circuitry to generate randomized values for setting a plurality of parameters, and a controller to adjust the variable load current provided to the cryptographic block based on the parameters and the current voltage of the cryptographic block. The controller to cause a decrease in the variable load current when the current voltage is above a high voltage threshold, an increase in the variable load current when the current voltage is below a low voltage threshold; and a maximization of the variable load current when the current voltage is below an undervoltage threshold. The cryptographic block may be implemented with arithmetic transformations.
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Patent Agency Ranking
公开(公告)号：US10825511B2
公开(公告)日：2020-11-03
申请号：US16417538
申请日：2019-05-20
Applicant: Intel Corporation
Inventor： Vivek De , Sanu Mathew , Sudhir Satpathy , Vikram Suresh , Raghavan Kumar
IPC: G11C11/419 , H04L9/32 , G09G5/00 , G06F7/58
Abstract: Techniques and mechanisms for changing a consistency with which a cell circuit (“cell”) settles into a given state. In one embodiment, a cell settles into a preferred state based on a relative polarity between respective voltages of a first rail and a second rail. Based on the preferred state, a hot carrier injection (HCI) stress is applied to change a likelihood of the cell settling into the preferred state. Applying the HCI stress includes driving off-currents of two PMOS transistors of the cell while the relative polarity is reversed. In another embodiment, a cell array comprises multiple cells which are each classified as being a respective one of a physically unclonable function (PUF) type or a random number generator (RNG) type. A cell is selected for biasing, and a stress is applied, based on each of: that cell's preferred state, that cell's classification, and another cell's classification.
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17.发明授权公开(公告)号：US10755242B2
公开(公告)日：2020-08-25
申请号：US15274200
申请日：2016-09-23
Applicant: Intel Corporation
Inventor： Vikram Suresh , Sudhir Satpathy , Sanu Mathew
Abstract: A Bitcoin mining hardware accelerator is described. A System on Chip implementing a Bitcoin mining hardware accelerator may include a processor core and a hardware accelerator coupled to the processor core, the hardware accelerator to mine digital currency. The hardware accelerator may include a first computational block, including a message digest datapath, wherein the first computational block is to: precompute a first summation of a 32-bit message (Wi), a 32-bit round constant (Ki), and a content of a first shifted state register (Gi−1), and store a result of the first summation in a state register (Hi). The Bitcoin mining hardware accelerator may further include a second computational block comprising a message scheduler datapath.
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18.发明申请公开(公告)号：US20190319799A1
公开(公告)日：2019-10-17
申请号：US16455921
申请日：2019-06-28
Applicant: Intel Corporation
Inventor： Vikram Suresh , Sanu Mathew , Manoj Sastry , Santosh Ghosh , Raghavan Kumar , Rafael Misoczki
Abstract: In one example an apparatus comprises a computer readable memory, a signature logic to generate a signature to be transmitted in association with a message, the signature logic to apply a hash-based signature scheme to the message using a private key to generate the signature comprising a public key, or a verification logic to verify a signature received in association with the message, the verification logic to apply the hash-based signature scheme to verify the signature using the public key, and an accelerator logic to apply a structured order to at least one set of inputs to the hash-based signature scheme. Other examples may be described.
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公开(公告)号：US20190042250A1
公开(公告)日：2019-02-07
申请号：US16003545
申请日：2018-06-08
Applicant: Intel Corporation
Inventor： Mark A. Anders , Himanshu Kaul , Sanu Mathew
Abstract: Disclosed embodiments relate to a variable format, variable sparsity matrix multiplication (VFVSMM) instruction. In one example, a processor includes fetch and decode circuitry to fetch and decode a VFVSMM instruction specifying locations of A, B, and C matrices having (M×K), (K×N), and (M×N) elements, respectively, execution circuitry, responsive to the decoded VFVSMM instruction, to: route each row of the specified A matrix, staggering subsequent rows, into corresponding rows of a (M×N) processing array, and route each column of the specified B matrix, staggering subsequent columns, into corresponding columns of the processing array, wherein each of the processing units is to generate K products of A-matrix elements and matching B-matrix elements having a same row address as a column address of the A-matrix element, and to accumulate each generated product with a corresponding C-matrix element.
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公开(公告)号：US09503256B2
公开(公告)日：2016-11-22
申请号：US14582707
申请日：2014-12-24
Applicant: Intel Corporation
Inventor： Kirk Yap , Gilbert Wolrich , Sudhir Satpathy , Sean Gulley , Vinodh Gopal , Sanu Mathew , Wajdi Feghali
CPC classification number: H04L9/0822 , G09C1/00 , H04L9/0631 , H04L2209/122
Abstract: Embodiments of an invention for SMS4 acceleration hardware are disclosed. In an embodiment, an apparatus includes SMS4 hardware and key transformation hardware. The SMS4 hardware is to execute a round of encryption and a round of key expansion. The key transformation hardware is to transform a key to provide for the SMS4 hardware to execute a round of decryption.
Abstract translation: 公开了用于SMS4加速硬件的发明的实施例。 在一个实施例中，一种装置包括SMS4硬件和密钥变换硬件。 SMS4硬件是执行一轮加密和一轮密钥扩展。 密钥转换硬件是转换密钥以提供SMS4硬件来执行一轮解密。
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