公开(公告)号：US11237614B2

公开(公告)日：2022-02-01

申请号：US16454378

申请日：2019-06-27

Applicant: Intel Corporation

Inventor： Malini K. Bhandaru ,  Eric J. Dehaemer ,  Scott P. Bobholz ,  Raghunandan Makaram ,  Vivek Garg

IPC: G06F1/324 ,  G06F1/26 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/3296 ,  G06F1/3225

Abstract: In one embodiment, a multicore processor includes cores that can independently execute instructions, each at an independent voltage and frequency. The processor may include a power controller having logic to provide for configurability of power management features of the processor. One such feature enables at least one core to operate at an independent performance state based on a state of a single power domain indicator present in a control register. Other embodiments are described and claimed.

公开(公告)号：US20160170468A1

公开(公告)日：2016-06-16

申请号：US15048189

申请日：2016-02-19

Applicant: Intel Corporation

Inventor： Malini K. Bhandaru ,  Eric J. Dehaemer ,  Scott P. Bobholz ,  Raghunandan Makaram ,  Vivek Garg

IPC: G06F1/32

CPC classification number: G06F1/324 ,  G06F1/26 ,  G06F1/3206 ,  G06F1/3225 ,  G06F1/3234 ,  G06F1/3243 ,  G06F1/3275 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

Abstract: In one embodiment, a multicore processor includes cores that can independently execute instructions, each at an independent voltage and frequency. The processor may include a power controller having logic to provide for configurability of power management features of the processor. One such feature enables at least one core to operate at an independent performance state based on a state of a single power domain indicator present in a control register. Other embodiments are described and claimed.

公开(公告)号：US09235244B2

公开(公告)日：2016-01-12

申请号：US13785259

申请日：2013-03-05

Applicant: Intel Corporation

Inventor： Malini K. Bhandaru ,  Eric J. Dehaemer ,  Scott P. Bobholz ,  Raghunandan Makaram ,  Vivek Garg

IPC: G06F1/26 ,  G06F1/32

CPC classification number: G06F1/324 ,  G06F1/26 ,  G06F1/3206 ,  G06F1/3225 ,  G06F1/3234 ,  G06F1/3243 ,  G06F1/3275 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

Abstract: In one embodiment, a multicore processor includes cores that can independently execute instructions, each at an independent voltage and frequency. The processor may include a power controller having logic to provide for configurability of power management features of the processor. One such feature enables at least one core to operate at an independent performance state based on a state of a single power domain indicator present in a control register. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，多核处理器包括可独立执行指令的核心，每个指令以独立的电压和频率进行。 处理器可以包括具有用于提供处理器的电源管理特征的可配置性的逻辑的功率控制器。 一种这样的特征使得至少一个核可以基于存在于控制寄存器中的单个功率域指示符的状态在独立的性能状态下操作。 描述和要求保护其他实施例。

公开(公告)号：US20240296051A1

公开(公告)日：2024-09-05

申请号：US18661103

申请日：2024-05-10

Applicant: Intel Corporation

Inventor： Jason W. Brandt ,  Deepak K. Gupta ,  Rodrigo Branco ,  Joseph Nuzman ,  Robert S. Chappell ,  Sergiu Ghetie ,  Wojciech Powiertowski ,  Jared W. Stark, IV ,  Ariel Sabba ,  Scott J. Cape ,  Hisham Shafi ,  Lihu Rappoport ,  Yair Berger ,  Scott P. Bobholz ,  Gilad Holzstein ,  Sagar V. Dalvi ,  Yogesh Bijlani

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3844 ,  G06F9/30101 ,  G06F9/3806

Abstract: Methods and apparatuses relating to mitigations for speculative execution side channels are described. Speculative execution hardware and environments that utilize the mitigations are also described. For example, three indirect branch control mechanisms and their associated hardware are discussed herein: (i) indirect branch restricted speculation (IBRS) to restrict speculation of indirect branches, (ii) single thread indirect branch predictors (STIBP) to prevent indirect branch predictions from being controlled by a sibling thread, and (iii) indirect branch predictor barrier (IBPB) to prevent indirect branch predictions after the barrier from being controlled by software executed before the barrier.

公开(公告)号：US20190317585A1

公开(公告)日：2019-10-17

申请号：US16454378

申请日：2019-06-27

Applicant: Intel Corporation

Inventor： Malini K. Bhandaru ,  Eric J. Dehaemer ,  Scott P. Bobholz ,  Raghunandan Makaram ,  Vivek Garg

IPC: G06F1/324 ,  G06F1/3234 ,  G06F1/3225 ,  G06F1/3296 ,  G06F1/26 ,  G06F1/3206

Abstract: In one embodiment, a multicore processor includes cores that can independently execute instructions, each at an independent voltage and frequency. The processor may include a power controller having logic to provide for configurability of power management features of the processor. One such feature enables at least one core to operate at an independent performance state based on a state of a single power domain indicator present in a control register. Other embodiments are described and claimed.

公开(公告)号：US20190171274A1

公开(公告)日：2019-06-06

申请号：US16271191

申请日：2019-02-08

Applicant: Intel Corporation

Inventor： Malini K. Bhandaru ,  Eric J. Dehaemer ,  Scott P. Bobholz ,  Raghunandan Makaram ,  Vivek Garg

IPC: G06F1/324 ,  G06F1/3234 ,  G06F1/3225 ,  G06F1/3296 ,  G06F1/26 ,  G06F1/3206

Abstract: In one embodiment, a multicore processor includes cores that can independently execute instructions, each at an independent voltage and frequency. The processor may include a power controller having logic to provide for configurability of power management features of the processor. One such feature enables at least one core to operate at an independent performance state based on a state of a single power domain indicator present in a control register. Other embodiments are described and claimed.

公开(公告)号：US10191532B2

公开(公告)日：2019-01-29

申请号：US15048055

申请日：2016-02-19

Applicant: Intel Corporation

Inventor： Malini K. Bhandaru ,  Eric J. Dehaemer ,  Scott P. Bobholz ,  Raghunandan Makaram ,  Vivek Garg

IPC: G06F1/32 ,  G06F1/26

Abstract: In one embodiment, a multicore processor includes cores that can independently execute instructions, each at an independent voltage and frequency. The processor may include a power controller having logic to provide for configurability of power management features of the processor. One such feature enables at least one core to operate at an independent performance state based on a state of a single power domain indicator present in a control register. Other embodiments are described and claimed.

公开(公告)号：US20160170478A1

公开(公告)日：2016-06-16

申请号：US15048055

申请日：2016-02-19

Applicant: Intel Corporation

Inventor： Malini K. Bhandaru ,  Eric J. Dehaemer ,  Scott P. Bobholz ,  Raghunandan Makaram ,  Vivek Garg

IPC: G06F1/32

CPC classification number: G06F1/324 ,  G06F1/26 ,  G06F1/3206 ,  G06F1/3225 ,  G06F1/3234 ,  G06F1/3243 ,  G06F1/3275 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

Abstract: In one embodiment, a multicore processor includes cores that can independently execute instructions, each at an independent voltage and frequency. The processor may include a power controller having logic to provide for configurability of power management features of the processor. One such feature enables at least one core to operate at an independent performance state based on a state of a single power domain indicator present in a control register. Other embodiments are described and claimed.