公开(公告)号：US11188335B2

公开(公告)日：2021-11-30

申请号：US17087536

申请日：2020-11-02

Applicant: Intel Corporation

Inventor： Regev Shemy ,  Zeev Sperber ,  Wajdi Feghali ,  Vinodh Gopal ,  Amit Gradstein ,  Simon Rubanovich ,  Sean Gulley ,  Ilya Albrekht ,  Jacob Doweck ,  Jose Yallouz ,  Ittai Anati

IPC: G06F9/30 ,  G06F9/38 ,  H04L9/06

Abstract: Systems, methods, and apparatuses relating to performing hashing operations on packed data elements are described. In one embodiment, a processor includes a decode circuit to decode a single instruction into a decoded single instruction, the single instruction including at least one first field that identifies eight 32-bit state elements A, B, C, D, E, F, G, and H for a round according to a SM3 hashing standard and at least one second field that identifies an input message; and an execution circuit to execute the decoded single instruction to: rotate state element C left by 9 bits to form a rotated state element C, rotate state element D left by 9 bits to form a rotated state element D, rotate state element G left by 19 bits to form a rotated state element G, rotate state element H left by 19 bits to form a rotated state element H, perform two rounds according to the SM3 hashing standard on the input message and state element A, state element B, rotated state element C, rotated state element D, state element E, state element F, rotated state element G, and rotated state element H to generate an updated state element A, an updated state element B, an updated state element E, and an updated state element F, and store the updated state element A, the updated state element B, the updated state element E, and the updated state element F into a location specified by the single instruction.

公开(公告)号：US10924591B2

公开(公告)日：2021-02-16

申请号：US16014690

申请日：2018-06-21

Applicant: INTEL CORPORATION

Inventor： Wajdi Feghali ,  Vinodh Gopal ,  Kirk Yap ,  Sean Gulley ,  Simon Peffers

IPC: H04L29/06 ,  H04L12/863

Abstract: Methods and apparatus for low-latency link compression schemes. Under the schemes, selected packets or messages are dynamically selected for compression in view of current transmit queue levels. The latency incurred during compression and decompression is not added to the data-path, but sits on the side of the transmit queue. The system monitors the queue depth and, accordingly, initiates compression jobs based on the depth. Different compression levels may be dynamically selected and used based on queue depth. Under various schemes, either packets or messages are enqueued in the transmit queue or pointers to such packets and messages are enqueued. Additionally, packets/message may be compressed prior to being enqueued, or after being enqueued, wherein an original uncompressed packet is replaced with a compressed packet. Compressed and uncompressed packets may be stored in queues or buffers and transmitted using a different numbers of transmit cycles based on their compression ratios. The schemes may be implemented to improve the effective bandwidth of various types of links, including serial links, bus-type links, and socket-to-socket links in multi-socket systems.

公开(公告)号：US09503256B2

公开(公告)日：2016-11-22

申请号：US14582707

申请日：2014-12-24

Applicant: Intel Corporation

Inventor： Kirk Yap ,  Gilbert Wolrich ,  Sudhir Satpathy ,  Sean Gulley ,  Vinodh Gopal ,  Sanu Mathew ,  Wajdi Feghali

IPC: H04L9/00 ,  H04L9/08 ,  H04L9/14

CPC classification number: H04L9/0822 ,  G09C1/00 ,  H04L9/0631 ,  H04L2209/122

Abstract: Embodiments of an invention for SMS4 acceleration hardware are disclosed. In an embodiment, an apparatus includes SMS4 hardware and key transformation hardware. The SMS4 hardware is to execute a round of encryption and a round of key expansion. The key transformation hardware is to transform a key to provide for the SMS4 hardware to execute a round of decryption.

Abstract translation: 公开了用于SMS4加速硬件的发明的实施例。 在一个实施例中，一种装置包括SMS4硬件和密钥变换硬件。 SMS4硬件是执行一轮加密和一轮密钥扩展。 密钥转换硬件是转换密钥以提供SMS4硬件来执行一轮解密。

公开(公告)号：US20150186139A1

公开(公告)日：2015-07-02

申请号：US14142745

申请日：2013-12-27

Applicant: Intel Corporation

Inventor： Gilbert M. Wolrich ,  Vinodh Gopal ,  Kirk S. Yap ,  Wajdi K. Feghali ,  Sean Gulley

IPC: G06F9/30

CPC classification number: G06F9/30145 ,  G06F9/30007 ,  G06F9/30036 ,  G09C1/00 ,  H04L9/0643 ,  H04L2209/122

Abstract: A processor includes a decode unit to receive an instruction to indicate a first source packed data operand and a second source packed data operand. The source operands each to include elements. The data elements to include information selected from messages and logical combinations of messages that is sufficient to evaluate: P1(Wj−16 XOR Wj−9 XOR(Wj−3

Abstract translation: 处理器包括解码单元，用于接收指示第一源打包数据操作数和第二源打包数据操作数的指令。 每个源操作数包含元素。 数据元素包括从消息中选择的信息和足以评估的消息的逻辑组合：P1（Wj-16 XOR Wj-9 XOR（Wj-3 <<<15））XOR（Wj-13 <<<7） XOR Wj-6 P1是置换函数，P1（X）= X XOR（X <<<15）XOR（X <<< 23）。 Wj-16，Wj-9，Wj-3，Wj-13和Wj-6是与SM3散列函数的压缩函数相关联的消息。 XOR是异或运算。 <<<是旋转操作。 与解码单元耦合的执行单元，其可响应于该指令操作以将结果打包数据存储在目的地存储位置中。 结果打包数据以包括要输入到压缩函数的第j个的Wj消息。