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    PATTERN MATCHING CIRCUIT
    11.
    发明申请
    PATTERN MATCHING CIRCUIT 审中-公开

    公开(公告)号：US20170286420A1

    公开(公告)日：2017-10-05

    申请号：US15085816

    申请日：2016-03-30

    Applicant: Intel Corporation

    Inventor： Amit Agarwal ,  Steven K. Hsu ,  Kaushik Vaidyanathan ,  Ram K. Krishnamurthy

    IPC: G06F17/30 ,  G06F21/56

    CPC classification number: G06F16/9014 ,  Y02D10/45

    Abstract: Embodiments include a pattern matching circuit that implements a Bloom filter including one or more hash functions. The hash functions may generate respective addresses corresponding to bits of a memory array. Various techniques for improving the area and/or power efficiency of the pattern matching circuit are disclosed. For example, a number of logic 1 bits per column of hash matrixes associated with the one or more hash functions may be restricted to a pre-defined number. A plurality of addresses generated by the hash functions may use the same column address to correspond to bits of a same column. A single read port memory may be used to simultaneously read two bits and generate an output signal that indicates whether the two bits are both a first logic value. Other embodiments may be described and claimed.

    SHARED CLOCK DUAL EDGE-TRIGGERED FLIP-FLOP CIRCUIT
    12.
    发明公开
    SHARED CLOCK DUAL EDGE-TRIGGERED FLIP-FLOP CIRCUIT 审中-公开

    公开(公告)号：US20240204782A1

    公开(公告)日：2024-06-20

    申请号：US18081907

    申请日：2022-12-15

    Applicant: Intel Corporation

    Inventor： Amit Agarwal ,  Steven K. Hsu ,  Ram Kumar Krishnamurthy

    IPC: H03K19/094 ,  H03K19/017 ,  H03K19/1776

    CPC classification number: H03K19/09425 ,  H03K19/01728 ,  H03K19/1776

    Abstract: Some embodiments include an apparatus having a flip-flop circuit, which can include a first tristate inverter, a second tristate inverter including an input node coupled to an input node of the first tristate inverter; a first additional inverter including, and a second additional inverter including an output node coupled to an output node of the first additional inverter; a first memory including a first memory node coupled to an output node of the second tristate inverter, and a first additional memory node coupled to an input node of the first additional inverter; and a second memory including a second memory node coupled to an output node of the first tristate inverter, and a second additional memory node coupled to an input node of the second additional inverter.

    Vectored flip-flop
    13.
    发明授权
    Vectored flip-flop 有权

    公开(公告)号：US10862462B2

    公开(公告)日：2020-12-08

    申请号：US16670830

    申请日：2019-10-31

    Applicant: Intel Corporation

    Inventor： Steven K. Hsu ,  Amit Agarwal ,  Simeon Realov

    IPC: H03K3/037 ,  H03K19/00

    Abstract: An apparatus is provided which comprises: a first flip-flop (FF) cell with a data path multiplexed with a scan-data path, wherein the scan-data path is independent of a min-delay buffer, wherein the first FF cell has a memory element formed of at least two inverting cells, wherein the two inverting cells are coupled together via a common node; and a second FF cell with a data path multiplexed with a scan-data path, wherein the scan-data path of the second FF cell is independent of a min-delay buffer, and wherein the scan-data path of the second FF cell is coupled to the common node of the first FF cell.

    Aging tolerant register file
    15.
    发明授权
    Aging tolerant register file 有权

    公开(公告)号：US10049724B2

    公开(公告)日：2018-08-14

    申请号：US15176069

    申请日：2016-06-07

    Applicant: Intel Corporation

    Inventor： Amit Agarwal ,  Steven K. Hsu ,  Sri Harsha Choday

    IPC: G11C11/00 ,  G11C11/419 ,  G11C5/14

    Abstract: An apparatus is provided which comprises: a first supply node to provide power supply; a column of memory cells coupled to the first supply node; a diode-connected device having a gate terminal coupled to the first supply node, and a source terminal coupled to second supply node; and a stack of devices coupled to the first supply node, wherein at least one device in the stack is coupled to the second supply node, and wherein the stack of devices is controllable according to an operation mode.

    ULTRA-LOW CLOCK POWER MULTI-BIT FLIP-FLOPS USING UNIDIRECTIONAL DEVICES
    18.
    发明申请
    ULTRA-LOW CLOCK POWER MULTI-BIT FLIP-FLOPS USING UNIDIRECTIONAL DEVICES 有权

    公开(公告)号：US20240429901A1

    公开(公告)日：2024-12-26

    申请号：US18340679

    申请日：2023-06-23

    Applicant: Intel Corporation

    Inventor： Steven K. Hsu ,  Amit Agarwal ,  Abhishek Anil Sharma ,  Ram K. Krishnamurthy

    IPC: H03K3/037 ,  H03K17/687

    Abstract: Embodiments herein relate to a multi-bit flip-flop circuit which uses unidirectional transistors to allow sharing of transistors among a set of flip-flops, while avoiding charge sharing within or between the flip-flops. Clock devices in the circuit can be shared to reduce the clock transistor gate capacitance and associated power consumption. The shared transistors can provide keeper circuits and/or tri-state inverters in a primary latch and a secondary latch in each flip-flop. One example implementation uses tri-state keeper sharing. Another example implementation uses tri-state keeper and/or pass gate sharing. Another example implementation uses pass gate sharing and no keeper.

    FUSED VOLTAGE LEVEL SHIFTING LATCH
    19.
    发明申请
    FUSED VOLTAGE LEVEL SHIFTING LATCH 审中-公开

    公开(公告)号：US20190280693A1

    公开(公告)日：2019-09-12

    申请号：US16335092

    申请日：2017-08-30

    Applicant: Intel Corporation

    Inventor： Steven K. Hsu ,  Amit Agarwal ,  Ram K. Krishnamurthy

    IPC: H03K19/0185 ,  H03K3/037

    Abstract: Some embodiments include apparatus and methods using an input stage and an output stage of a circuit. The input stage operates to receive an input signal and a clock signal and to provide an internal signal at an internal node based at least in part on the input signal. The input signal has levels in a first voltage range. The internal signal has levels in a second voltage range greater than the first voltage range. The output stage operates to receive the internal signal, the clock signal, and an additional signal generated based on the input signal. The output stage provides an output signal based at least in part on the input signal and the additional signal. The output signal has a third voltage range greater than the first voltage range.

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