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    High Work Function, Manufacturable Top Electrode
    12.
    发明申请
    High Work Function, Manufacturable Top Electrode 有权
    高功能，可制造顶电极

    公开(公告)号：US20140183697A1

    公开(公告)日：2014-07-03

    申请号：US13737263

    申请日：2013-01-09

    Applicant: INTERMOLECULAR, INC.

    Inventor： Sandra G. Malhotra ,  Hanhong Chen ,  Wim Deweerd ,  Arthur Gevondyan ,  Hiroyuki Ode

    IPC: H01L29/92

    CPC classification number: H01L29/92 ,  H01L28/65 ,  H01L28/75 ,  H01L51/0021 ,  H01L51/5206

    Abstract: Provided are MIM DRAM capacitors and methods of forming thereof. A MIM DRAM capacitor may include an electrode layer formed from a high work function material (e.g., greater than about 5.0 eV). This layer may be used to reduce the leakage current through the capacitor. The capacitor may also include another electrode layer having a high conductivity base portion and a conductive metal oxide portion. The conductive metal oxide portion serves to promote the growth of the high k phase of the dielectric layer.

    Abstract translation: 提供MIM DRAM电容器及其形成方法。 MIM DRAM电容器可以包括由高功函数材料（例如，大于约5.0eV）形成的电极层。 该层可用于减少通过电容器的漏电流。 电容器还可以包括具有高导电性基底部分和导电金属氧化物部分的另一个电极层。 导电金属氧化物部分用于促进电介质层的高k相的生长。

    Method for producing MIM capacitors with high K dielectric materials and non-noble electrodes
    13.
    发明授权
    Method for producing MIM capacitors with high K dielectric materials and non-noble electrodes 有权
    用于制造具有高K电介质材料和非贵金属电极的MIM电容器的方法

    公开(公告)号：US08674479B2

    公开(公告)日：2014-03-18

    申请号：US13902679

    申请日：2013-05-24

    Applicant: Intermolecular, Inc. ,  Elpida Memory, Inc.

    Inventor： Hanhong Chen ,  Pragati Kumar

    IPC: H01L21/302

    CPC classification number: H01L28/60 ,  H01L28/40

    Abstract: A method of producing a Metal-Insulator-Metal (MIM) capacitor stack through doping to achieve low current leakage and low equivalent oxide thickness is disclosed. A high K dielectric material is deposited on a non-noble electrode; the dielectric material is doped with oxides from group IIA. The dopant increases the barrier height of metal/insulator interface and neutralizes free electrons in dielectric material, therefore reduces the leakage current of MIM capacitor. The electrode may also be doped to increase work function while maintaining a rutile crystalline structure. The method thereby enhances the performance of DRAM MIM capacitor.

    Abstract translation: 公开了一种通过掺杂制造金属 - 绝缘体 - 金属（MIM）电容器堆叠以实现低电流泄漏和低等效氧化物厚度的方法。 高K电介质材料沉积在非贵金属电极上; 电介质材料掺杂有IIA族的氧化物。 掺杂剂增加了金属/绝缘体界面的势垒高度，并且中和了介电材料中的自由电子，从而降低了MIM电容器的漏电流。 电极也可以掺杂以增加功函数，同时保持金红石晶体结构。 该方法从而增强了DRAM MIM电容器的性能。

    Asymmetric MIM capacitor for DRAM devices
    14.
    发明授权
    Asymmetric MIM capacitor for DRAM devices 有权
    用于DRAM器件的不对称MIM电容器

    公开(公告)号：US08575671B2

    公开(公告)日：2013-11-05

    申请号：US13692460

    申请日：2012-12-03

    Applicant: Intermolecular, Inc. ,  Elpida Memory, Inc.

    Inventor： Hanhong Chen ,  Hiroyuki Ode

    IPC: H01L27/108 ,  H01L29/94

    CPC classification number: H01L28/65 ,  H01L27/10805 ,  H01L28/75

    Abstract: A bilayer second electrode for a MIM DRAM capacitor is formed wherein the layer of the electrode that is in contact with the dielectric layer (i.e. bottom layer) has a composition that is resistant to oxidation during subsequent anneal steps and have rutile templating capability. Examples include SnO2 and RuO2. The capacitor stack including the bottom layer is subjected to a PMA treatment to reduce the oxygen vacancies in the dielectric layer and reduce the interface states at the dielectric/second electrode interface. The other component of the bilayer (i.e. top layer) is a high work function, high conductivity metal or conductive metal compound.

    Abstract translation: 形成用于MIM DRAM电容器的双层第二电极，其中与电介质层（即底层）接触的电极层具有在随后的退火步骤期间耐氧化的组成并具有金红石模板能力。 实例包括SnO 2和RuO 2。 包括底层的电容器堆叠经受PMA处理以减少电介质层中的氧空位并降低电介质/第二电极界面处的界面态。 双层的另一组分（即顶层）是高功函数，高导电性金属或导电金属化合物。

    Blocking layers for leakage current reduction in DRAM devices
    15.
    发明授权
    Blocking layers for leakage current reduction in DRAM devices 有权
    阻塞层用于DRAM器件的漏电流降低

    公开(公告)号：US08574999B2

    公开(公告)日：2013-11-05

    申请号：US13738865

    申请日：2013-01-10

    Applicant: Intermolecular Inc. ,  Elpida Memory, Inc

    Inventor： Sandra G. Malhotra ,  Hanhong Chen ,  Wim Y. Deweerd ,  Hiroyuki Ode

    IPC: H01L21/20 ,  H01L29/94

    CPC classification number: H01L28/60 ,  H01L27/10852 ,  H01L28/40

    Abstract: A method for forming a DRAM MIM capacitor stack having low leakage current involves the use of a first electrode that serves as a template for promoting the high k phase of a subsequently deposited dielectric layer. The high k dielectric layer comprises a doped material that can be crystallized after a subsequent annealing treatment. An amorphous blocking is formed on the dielectric layer. The thickness of the blocking layer is chosen such that the blocking layer remains amorphous after a subsequent annealing treatment. A second electrode layer compatible with the blocking layer is formed on the blocking layer.

    Abstract translation: 用于形成具有低泄漏电流的DRAM MIM电容器堆叠的方法涉及使用用作促进随后沉积的介电层的高k相的模板的第一电极。 高k电介质层包括可在随后的退火处理后结晶的掺杂材料。 在电介质层上形成无定形阻挡层。 选择阻挡层的厚度使得在随后的退火处理之后阻挡层保持无定形。 在阻挡层上形成与阻挡层相容的第二电极层。

    DRAM MIMCAP Stack with MoO2 Electrode
    18.
    发明申请
    DRAM MIMCAP Stack with MoO2 Electrode 审中-公开
    DRAM MIMCAP堆叠与MoO2电极

    公开(公告)号：US20160133691A1

    公开(公告)日：2016-05-12

    申请号：US14534816

    申请日：2014-11-06

    Applicant: Intermolecular, Inc.

    Inventor： Prashant B. Phatak ,  Hanhong Chen ,  Tony P. Chiang ,  Chien-Lan Hsueh ,  Monica Mathur

    IPC: H01L49/02 ,  H01L27/108

    CPC classification number: H01L28/75 ,  H01L27/1085 ,  H01L28/40 ,  H01L28/60

    Abstract: Steps are taken to ensure that the bulk dielectric layer exhibits a crystalline phase before the deposition of a second electrode layer. The crystalline phase of the bulk dielectric layer facilitates the crystallization of the second electrode layer at lower temperature during a subsequent anneal treatment. In some embodiments, one or more interface layers are inserted between the bulk dielectric layer and the first electrode layer and/or the second electrode layer. The interface layers may act as an oxygen sink, facilitate the crystallization of the electrode layer at lower temperature during a subsequent anneal treatment, or provide barriers to leakage current through the film stack.

    Abstract translation: 采取步骤以确保在沉积第二电极层之前体积电介质层呈现结晶相。 在随后的退火处理期间，体电介质层的结晶相有助于在较低温度下第二电极层的结晶。 在一些实施例中，一个或多个界面层插入在体电介质层和第一电极层和/或第二电极层之间。 界面层可以充当氧气沉淀器，在随后的退火处理期间促进电极层在较低温度下的结晶，或者提供通过膜堆叠的漏电流的障碍。

    DRAM MIM capacitor using non-noble electrodes
    19.
    发明授权
    DRAM MIM capacitor using non-noble electrodes 有权

    公开(公告)号：US09281357B2

    公开(公告)日：2016-03-08

    申请号：US14599843

    申请日：2015-01-19

    Applicant: Intermolecular, Inc. ,  Elpida Memory, Inc

    Inventor： Hanhong Chen ,  David Chi ,  Imran Hashim ,  Mitsuhiro Horikawa ,  Sandra G. Malhotra

    IPC: H01L49/02 ,  H01L27/108

    CPC classification number: H01L28/56 ,  H01L27/108 ,  H01L27/1085 ,  H01L28/40 ,  H01L28/75 ,  H01L28/82

    Abstract: A method for forming a capacitor stack includes forming a first bottom electrode layer including a conductive metal nitride material. A second bottom electrode layer is formed above the first bottom electrode layer. The second bottom electrode layer includes a conductive metal oxide material, wherein the crystal structure of the conductive metal oxide material promotes a desired high-k crystal phase of a subsequently deposited dielectric layer. A dielectric layer is formed above the second bottom electrode layer. Optionally, an oxygen-rich metal oxide layer is formed above the dielectric layer. Optionally, a third top electrode layer is formed above the oxygen-rich metal oxide layer. The third top electrode layer includes a conductive metal oxide material. A fourth top electrode layer is formed above the third top electrode layer. The fourth top electrode layer includes a conductive metal nitride material.

    High work function, manufacturable top electrode
    20.
    发明授权
    High work function, manufacturable top electrode 有权
    高功能，可制造顶电极

    公开(公告)号：US09224878B2

    公开(公告)日：2015-12-29

    申请号：US13727962

    申请日：2012-12-27

    Applicant: Intermolecular, Inc. ,  Elpida Memory, Inc

    Inventor： Sandra G. Malhotra ,  Hanhong Chen ,  Wim Deweerd ,  Arthur Gevondyan ,  Hiroyuki Ode

    IPC: H01L21/20 ,  H01L29/92 ,  H01L49/02 ,  H01L51/52 ,  H01L51/00

    CPC classification number: H01L29/92 ,  H01L28/65 ,  H01L28/75 ,  H01L51/0021 ,  H01L51/5206

    Abstract: Provided are MIM DRAM capacitors and methods of forming thereof. A MIM DRAM capacitor may include an electrode layer formed from a high work function material (e.g., greater than about 5.0 eV). This layer may be used to reduce the leakage current through the capacitor. The capacitor may also include another electrode layer having a high conductivity base portion and a conductive metal oxide portion. The conductive metal oxide portion serves to promote the growth of the high k phase of the dielectric layer.

    Abstract translation: 提供MIM DRAM电容器及其形成方法。 MIM DRAM电容器可以包括由高功函数材料（例如，大于约5.0eV）形成的电极层。 该层可用于减少通过电容器的漏电流。 电容器还可以包括具有高导电性基底部分和导电金属氧化物部分的另一个电极层。 导电金属氧化物部分用于促进电介质层的高k相的生长。

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