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    Process for improving capacitance extraction performance
    13.
    发明授权
    Process for improving capacitance extraction performance 有权

    公开(公告)号：US10354041B2

    公开(公告)日：2019-07-16

    申请号：US15832249

    申请日：2017-12-05

    Applicant: International Business Machines Corporation

    Inventor： Robert J. Allen ,  Susan E. Cellier ,  Lewis W. Dewey, III ,  Anthony D. Hagin ,  Adam P. Matheny ,  Ronald D. Rose ,  David J. Widiger

    IPC: G06F17/50

    Abstract: Disclosed is a method for improving capacitance extraction performance in a circuit, the method including mapping, via a computing resource, a first layout including a plurality of wiring paths, selecting at least one target wire from the plurality of wiring paths, selecting at least one group of wires running orthogonally to the at least one target wire, identifying and selecting within the at least one group at least one set of two or more wires that are combinable for representation as a single merged wire, mapping a second layout, via the computing resource, and representing the at least one set of two or more wires as the single merged wire in said second layout, analyzing parasitic capacitance between the at least one target wire and the at least one group of wires using the second layout, and manufacturing the circuit using information from the analyzing of parasitic capacitance.

    PROCESS FOR IMPROVING CAPACITANCE EXTRACTION PERFORMANCE
    15.
    发明申请
    PROCESS FOR IMPROVING CAPACITANCE EXTRACTION PERFORMANCE 有权

    公开(公告)号：US20170161422A1

    公开(公告)日：2017-06-08

    申请号：US14962185

    申请日：2015-12-08

    Applicant: International Business Machines Corporation

    Inventor： Robert J. Allen ,  Susan E. Cellier ,  Lewis W. Dewey, III ,  Anthony D. Hagin ,  Adam P. Matheny ,  Ronald D. Rose ,  David J. Widiger

    IPC: G06F17/50

    CPC classification number: G06F17/5077 ,  G06F17/5081 ,  G06F2217/82

    Abstract: Disclosed is a method for improving capacitance extraction performance in a circuit, the method including mapping, via a computing resource, a first layout including a plurality of wiring paths, selecting at least one target wire from the plurality of wiring paths, selecting at least one group of wires running orthogonally to the at least one target wire, identifying and selecting within the at least one group at least one set of two or more wires that are combinable for representation as a single merged wire, mapping a second layout, via the computing resource, and representing the at least one set of two or more wires as the single merged wire in said second layout, analyzing parasitic capacitance between the at least one target wire and the at least one group of wires using the second layout, and manufacturing the circuit using information from the analyzing of parasitic capacitance.

    Incremental parasitic extraction for coupled timing and power optimization
    16.
    发明授权
    Incremental parasitic extraction for coupled timing and power optimization 有权

    公开(公告)号：US10169526B2

    公开(公告)日：2019-01-01

    申请号：US15811826

    申请日：2017-11-14

    Applicant: International Business Machines Corporation

    Inventor： Kerim Kalafala ,  Tsz-Mei Ko ,  Ravichander Ledalla ,  Alice H. Lee ,  Adam P. Matheny ,  Jose L. Neves ,  Gregory M. Schaeffer

    IPC: G06F17/50

    Abstract: An incremental parasitic extraction system includes a noise analysis module configured to perform a first noise analysis on at least one first net with respect to at least one aggressor net. The incremental parasitic extraction system further includes an optimizer module and an extraction module. The optimizer module performs a first optimization activity on the at least one first net based on results of the first noise analysis. The optimizer module further generates a first invalidation list based on the first optimization activity, and a second invalidation list based on a type of the first optimization action so as to add the second invalidation list to the first invalidation list. The extraction module processes the first and second invalidation lists and performs an extraction and noise analysis process on the first and second invalidation lists so as to determine at least one new RC network and associated noise analysis results.

    Methods and computer program products for via capacitance extraction
    17.
    发明授权
    Methods and computer program products for via capacitance extraction 有权

    公开(公告)号：US10169516B2

    公开(公告)日：2019-01-01

    申请号：US14964863

    申请日：2015-12-10

    Applicant: International Business Machines Corporation

    Inventor： Susan E. Cellier ,  Lewis W. Dewey, III ,  Anthony D. Hagin ,  Adam P. Matheny ,  Ronald D. Rose ,  David J. Widiger

    IPC: G06F17/50

    Abstract: Embodiments include methods, processing systems and computer program products for extracting via capacitance. Aspects include placing various shapes of target nets of an IC into a Cshapes collection and a CshapesVia collection, processing the shapes in these collections and placing the processed shapes into a Ctile collection and a CtilesVia collection, and extracting via capacitance of the target nets through each of Cshapes, CshapesVia, Ctiles, and CtilesVia collections. In exemplary embodiments, the processing operation includes: reducing the complexity of the shapes in the shape collections, removing all overhang shapes, and all overlapped shapes from the shape collections, and unioning the shapes in the Cshapes collection and the CshapesVia collection, respectively. Unioning operation includes: unioning shapes from Cshapes collection into a non-overlapping Ctiles collection, unioning shapes from CshapesVia collection into a non-overlapping CtileVia collection, computing the tile intersections of Cshapes collection and CshapesVia collection, and removing intersections from CshapesVia collection.

    Process for improving capacitance extraction performance
    19.
    发明授权
    Process for improving capacitance extraction performance 有权

    公开(公告)号：US09886541B2

    公开(公告)日：2018-02-06

    申请号：US14962185

    申请日：2015-12-08

    Applicant: International Business Machines Corporation

    Inventor： Robert J. Allen ,  Susan E. Cellier ,  Lewis W. Dewey, III ,  Anthony D. Hagin ,  Adam P. Matheny ,  Ronald D. Rose ,  David J. Widiger

    IPC: G06F17/50

    CPC classification number: G06F17/5077 ,  G06F17/5081 ,  G06F2217/82

    Abstract: Disclosed is a method for improving capacitance extraction performance in a circuit, the method including mapping, via a computing resource, a first layout including a plurality of wiring paths, selecting at least one target wire from the plurality of wiring paths, selecting at least one group of wires running orthogonally to the at least one target wire, identifying and selecting within the at least one group at least one set of two or more wires that are combinable for representation as a single merged wire, mapping a second layout, via the computing resource, and representing the at least one set of two or more wires as the single merged wire in said second layout, analyzing parasitic capacitance between the at least one target wire and the at least one group of wires using the second layout, and manufacturing the circuit using information from the analyzing of parasitic capacitance.

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