公开(公告)号：US11176308B1

公开(公告)日：2021-11-16

申请号：US16906874

申请日：2020-06-19

Applicant: International Business Machines Corporation

Inventor： David J. Widiger ,  Steven Joseph Kurtz ,  Susan Elizabeth Cellier ,  Lewis William Dewey, III ,  Ronald Dennis Rose

IPC: G06F30/398 ,  G06F119/02 ,  G06F119/12 ,  G06F119/18 ,  G06F30/39

Abstract: An integrated circuit includes a target wiring layer, a first adjacent wiring layer above the target wiring layer, and a second adjacent wiring layer below the target wiring layer. Each adjacent wiring layer including crossing wires orthogonal to the target wiring layer. Modify a putative design of the integrated circuit by selecting a target wire; identifying lateral neighbors of the target wire; defining regions of the target wire where the lateral neighbors are homogeneous in cross-section; for each region of the target wire, calculating a wire pattern for the crossing wires; identifying segments within above and below portions of the wire pattern; for each above and below segment pair, obtaining a per-unit-length capacitance from a reduced pattern database; extracting a total parasitic capacitance from the per-unit-length pattern capacitances; and in response to an assessment of the impact of the total parasitic capacitance on circuit performance, producing a modified design.

公开(公告)号：US10929581B2

公开(公告)日：2021-02-23

申请号：US16432805

申请日：2019-06-05

Applicant: International Business Machines Corporation

Inventor： Steven Joseph Kurtz ,  Ronald D. Rose ,  David J. Widiger

IPC: G06F30/30 ,  G06F119/12 ,  G06F119/10

Abstract: The accuracy of electronic design automation is increased by determining whether fill wires in a putative integrated circuit design should be effectively grounded or floating. For each signal wire in the putative design adjacent to the fill wires, a signal sensitivity value, which represents sensitivity of a given one of the plurality of signal wires to noise and timing, is determined. For each one of the fill wires, a fill sensitivity value is determined by: identifying coupling of each one of the fill wires to the adjacent signal wires; and calculating the fill sensitivity value as a combination of the signal sensitivity values of each of the adjacent signal wires for which the coupling has been identified. At least a portion of the fill wires are selectively effectively grounded based on the fill sensitivity value, to obtain a modified design.

公开(公告)号：US10685168B2

公开(公告)日：2020-06-16

申请号：US16169223

申请日：2018-10-24

Applicant: International Business Machines Corporation

Inventor： David J. Widiger ,  Ronald D. Rose ,  Lewis W. Dewey, III ,  Harold E. Reindel

IPC: G06F30/30 ,  G06F17/50 ,  G06F30/398 ,  G06F30/367 ,  G06F30/394 ,  G06F30/3312 ,  G06F119/06 ,  G06F119/10

Abstract: A system and method to perform capacitance extraction involves defining a location of signal wires and floating metal of an integrated circuit design. The method includes designating one of the signal wires as a target wire, defining a first area within which first capacitances between the target wire and the floating metal and other signal wires are determined, defining a second area, within which second capacitances between floating metal within the first area and the floating metal and the other signal wires not within the first area are determined, and generating an intermediate capacitive network. The intermediate capacitive network includes the target wire, the floating metal, and the other signal wires within the second area, the first capacitances and the second capacitances. A capacitive network is generated from the intermediate capacitive network. The first capacitances and the second capacitances are used to generate third capacitance values of the capacitive network.

公开(公告)号：US20200134129A1

公开(公告)日：2020-04-30

申请号：US16169223

申请日：2018-10-24

Applicant: International Business Machines Corporation

Inventor： David J. Widiger ,  Ronald D. Rose ,  Lewis W. Dewey, III ,  Harold E. Reindel

IPC: G06F17/50

Abstract: A system and method to perform capacitance extraction involves defining a location of signal wires and floating metal of an integrated circuit design. The method includes designating one of the signal wires as a target wire, defining a first area within which first capacitances between the target wire and the floating metal and other signal wires are determined, defining a second area, within which second capacitances between floating metal within the first area and the floating metal and the other signal wires not within the first area are determined, and generating an intermediate capacitive network. The intermediate capacitive network includes the target wire, the floating metal, and the other signal wires within the second area, the first capacitances and the second capacitances. A capacitive network is generated from the intermediate capacitive network. The first capacitances and the second capacitances are used to generate third capacitance values of the capacitive network.

公开(公告)号：US20180082009A1

公开(公告)日：2018-03-22

申请号：US15832249

申请日：2017-12-05

Applicant: International Business Machines Corporation

Inventor： Robert J. Allen ,  Susan E. Cellier ,  Lewis W. Dewey, III ,  Anthony D. Hagin ,  Adam P. Matheny ,  Ronald D. Rose ,  David J. Widiger

IPC: G06F17/50

CPC classification number: G06F17/5077 ,  G06F17/5081 ,  G06F2217/82

Abstract: Disclosed is a method for improving capacitance extraction performance in a circuit, the method including mapping, via a computing resource, a first layout including a plurality of wiring paths, selecting at least one target wire from the plurality of wiring paths, selecting at least one group of wires running orthogonally to the at least one target wire, identifying and selecting within the at least one group at least one set of two or more wires that are combinable for representation as a single merged wire, mapping a second layout, via the computing resource, and representing the at least one set of two or more wires as the single merged wire in said second layout, analyzing parasitic capacitance between the at least one target wire and the at least one group of wires using the second layout, and manufacturing the circuit using information from the analyzing of parasitic capacitance.

公开(公告)号：US20220035983A1

公开(公告)日：2022-02-03

申请号：US16945482

申请日：2020-07-31

Applicant: International Business Machines Corporation

Inventor： David J. Widiger ,  Steven Joseph Kurtz ,  Lewis William Dewey, III ,  Susan Elizabeth Cellier ,  Ronald Dennis Rose

IPC: G06F30/392

Abstract: An effective spacing is calculated for each physical spacing between two or more neighbor nets of a target net. Segment boundaries are determined based on the calculated effective spacing to define segments for the target net and one of the segments is selected. A metal configuration for the selected segment is identified and a table of capacitance per-unit-length is accessed for the identified metal configuration to return an above capacitance value, a below capacitance value, a left-side capacitance value, and a right-side capacitance value for the corresponding segment, the table comprising at least a two-dimensional (2D) table. The capacitance values are scaled based on a corresponding segment length determined from the calculated effective spacing. The selecting, identifying, accessing and scaling operations are repeated for each remaining segment of the target net. Optionally, the above, below, left, and right capacitance values for all segments of the target net are summed.

公开(公告)号：US20170169151A1

公开(公告)日：2017-06-15

申请号：US14964863

申请日：2015-12-10

Applicant: International Business Machines Corporation

Inventor： Susan E. Cellier ,  Lewis W. Dewey, III ,  Anthony D. Hagin ,  Adam P. Matheny ,  Ronald D. Rose ,  David J. Widiger

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5036 ,  G06F17/5068 ,  G06F2217/82

Abstract: Embodiments include methods, processing systems and computer program products for extracting via capacitance. Aspects include placing various shapes of target nets of an IC into a Cshapes collection and a CshapesVia collection, processing the shapes in these collections and placing the processed shapes into a Ctile collection and a CtilesVia collection, and extracting via capacitance of the target nets through each of Cshapes, CshapesVia, Ctiles, and CtilesVia collections. In exemplary embodiments, the processing operation includes: reducing the complexity of the shapes in the shape collections, removing all overhang shapes, and all overlapped shapes from the shape collections, and unioning the shapes in the Cshapes collection and the CshapesVia collection, respectively. Unioning operation includes: unioning shapes from Cshapes collection into a non-overlapping Ctiles collection, unioning shapes from CshapesVia collection into a non-overlapping CtileVia collection, computing the tile intersections of Cshapes collection and CshapesVia collection, and removing intersections from CshapesVia collection.

公开(公告)号：US20130246992A1

公开(公告)日：2013-09-19

申请号：US13887491

申请日：2013-05-06

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ibrahim M. Elfadel ,  Tarek Ali El Moselhy ,  David J. Widiger

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5036 ,  G06F17/5068 ,  G06F17/5081 ,  G06F2217/12 ,  H05K2201/09781

Abstract: A computer system selects a signal conductor from an electronic circuit design layout and assigns a first potential to the selected signal conductor. Next, the computer system assigns a second potential to other signal conductors included in the electronic circuit design layout. The computer system then selects a metal fill from the electronic circuit design layout, which is void from carrying an electrical signal, and generates a zero charge equation for the selected metal fill. The zero charge equation establishes that a total charge residing on the selected metal fill is equal to zero. The computer system includes the zero charge equation in a system of equations, which includes grid point potential equations, and solves the system of equations. In turn, the computer system computes capacitance values for the signal conductors based upon the system of equation solutions, and simulates the electronic circuit design layout using the computed capacitance values.

Abstract translation: 计算机系统从电子电路设计布局中选择信号导体，并将第一电位分配给所选择的信号导体。 接下来，计算机系统向包括在电子电路设计布局中的其它信号导体分配第二电位。 然后，计算机系统从电子电路设计布局中选择一个金属填充物，该电子设备布局无法携带电信号，并为所选择的金属填充产生零电荷方程。 零电荷方程式确定驻留在所选金属填充上的总电荷等于零。 计算机系统包括方程组中的零电荷方程，其包括网格点电位方程，并求解方程组。 反过来，计算机系统基于方程解的系统来计算信号导体的电容值，并使用计算的电容值来模拟电子电路设计布局。

公开(公告)号：US20250156622A1

公开(公告)日：2025-05-15

申请号：US18507309

申请日：2023-11-13

Applicant: International Business Machines Corporation

Inventor： David J. Widiger ,  Ronald Dennis Rose ,  Steven Joseph Kurtz ,  Susan Elizabeth Cellier ,  Lewis William Dewey, III

IPC: G06F30/398 ,  G06F30/367 ,  G06F30/392

Abstract: A method for analyzing an area of a target wire includes determining a wiring pattern for performing pattern-based 3D capacitance extraction, determining the target wire included in the wiring pattern, and dividing the target wire into segments based on effective spaces of various crossing wires. The method further includes determining a capacitance analysis that applies for each of the segments, determining a plurality of capacitance results corresponding to the capacitance analysis applied to each of the segments, and accumulating the plurality of capacitance results to extract a total capacitance corresponding to the target wire. The segments are based on an effective spacing of crossing wires, which are located above the target wire and extend across the target wire. The effective spaces are determined using a parameterized function that implements at least two adjustable parameters that are set to obtain the wiring pattern using a fitting process.

公开(公告)号：US10169516B2

公开(公告)日：2019-01-01

申请号：US14964863

申请日：2015-12-10

Applicant: International Business Machines Corporation

Inventor： Susan E. Cellier ,  Lewis W. Dewey, III ,  Anthony D. Hagin ,  Adam P. Matheny ,  Ronald D. Rose ,  David J. Widiger

IPC: G06F17/50

Abstract: Embodiments include methods, processing systems and computer program products for extracting via capacitance. Aspects include placing various shapes of target nets of an IC into a Cshapes collection and a CshapesVia collection, processing the shapes in these collections and placing the processed shapes into a Ctile collection and a CtilesVia collection, and extracting via capacitance of the target nets through each of Cshapes, CshapesVia, Ctiles, and CtilesVia collections. In exemplary embodiments, the processing operation includes: reducing the complexity of the shapes in the shape collections, removing all overhang shapes, and all overlapped shapes from the shape collections, and unioning the shapes in the Cshapes collection and the CshapesVia collection, respectively. Unioning operation includes: unioning shapes from Cshapes collection into a non-overlapping Ctiles collection, unioning shapes from CshapesVia collection into a non-overlapping CtileVia collection, computing the tile intersections of Cshapes collection and CshapesVia collection, and removing intersections from CshapesVia collection.