公开(公告)号：US11010210B2

公开(公告)日：2021-05-18

申请号：US16527424

申请日：2019-07-31

Applicant: International Business Machines Corporation

Inventor： Robert J. Sonnelitter, III ,  Michael Fee ,  Craig R. Walters ,  Arthur O'Neill ,  Matthias Klein

IPC: G06F9/52 ,  G06F9/48 ,  G06F12/0802 ,  G06F9/54 ,  G06F9/38

Abstract: Embodiments of the present invention are directed to a computer-implemented method for controller address contention assumption. A non-limiting example computer-implemented method includes a shared controller receiving a fetch request for data from a first requesting agent, the receiving via at least one intermediary controller. The shared controller performs an address compare using a memory address of the data. In response to the memory address matching a memory address stored in the shared controller, the shared controller acknowledges the at least one intermediary controller's fetch request, wherein upon acknowledgement, the at least one intermediary controller resets. In response to release of the data by a second requesting agent, the shared controller transmits the data to the first requesting agent.

公开(公告)号：US20210034438A1

公开(公告)日：2021-02-04

申请号：US16527424

申请日：2019-07-31

Applicant: International Business Machines Corporation

Inventor： Robert J. Sonnelitter, III ,  Michael Fee ,  Craig R. Walters ,  Arthur O'Neill ,  Matthias Klein

IPC: G06F9/52 ,  G06F9/48 ,  G06F9/38 ,  G06F9/54 ,  G06F12/0802

Abstract: Embodiments of the present invention are directed to a computer-implemented method for controller address contention assumption. A non-limiting example computer-implemented method includes a shared controller receiving a fetch request for data from a first requesting agent, the receiving via at least one intermediary controller. The shared controller performs an address compare using a memory address of the data. In response to the memory address matching a memory address stored in the shared controller, the shared controller acknowledges the at least one intermediary controller's fetch request, wherein upon acknowledgement, the at least one intermediary controller resets. In response to release of the data by a second requesting agent, the shared controller transmits the data to the first requesting agent.

公开(公告)号：US10833707B2

公开(公告)日：2020-11-10

申请号：US16273370

申请日：2019-02-12

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Glenn Gilda ,  Arthur O'Neill

IPC: G11C29/52 ,  H03M13/17 ,  G06F11/10 ,  H03M13/15

Abstract: Embodiments include methods, systems and circuits for operating an error trapping logic circuit in a memory device. Aspects include receiving, during a first clock cycle, data and check bits for the data from a memory location and determining, during the first clock cycle, whether the data includes any error by calculating an error syndrome from the data and the check bits. Aspects also include determining, during a second clock cycle, a type of the error based on a full decoding of the error syndrome. Aspects further include determining whether to store the data, the check bits and the error syndrome in trap registers of the error trapping logic circuit based on an operating mode of the error trapping logic circuit and the type of the error.

公开(公告)号：US10601448B2

公开(公告)日：2020-03-24

申请号：US15830526

申请日：2017-12-04

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Glenn Gilda ,  Patrick J. Meaney ,  Arthur O'Neill ,  Barry M. Trager

IPC: H03M13/15 ,  H03M13/00

Abstract: Systems, methods, and computer-readable media are disclosed for performing reduced latency error decoding using a reduced latency symbol error correction decoder that utilizes enumerated parallel multiplication in lieu of division and replaces general multiplication with constant multiplication. The use of parallel multiplication in lieu of division can provide reduced latency and replacement of general multiplication with constant multiplication allows for logic reduction. In addition, the reduced symbol error correction decoder can utilize decode term sharing which can yield a further reduction in decoder logic and a further latency improvement.