公开(公告)号：US20180294354A1

公开(公告)日：2018-10-11

申请号：US16006905

申请日：2018-06-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： HEMANTH JAGANNATHAN ,  SHOGO MOCHIZUKI

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/167 ,  H01L21/02 ,  H01L21/306 ,  H01L29/66

Abstract: Low temperature epitaxial silicon deposition for forming the top source or drain regions of VTFET structures. The methods generally include epitaxially growing a silicon layer with a dopant at a temperature less 500° C. on a first surface and an additional surface to form a single crystalline silicon on the first surface and a polysilicon or amorphous silicon on the additional surface. The epitaxially grown silicon layer is then exposed to an etchant include HCl and germane at a temperature less than 500° C. for a period of time effective to selectively remove the polysilicon/amorphous silicon on the additional surface and form a germanium diffused region on and in an outer surface of the single crystalline silicon formed on the first surface.

公开(公告)号：US20180122937A1

公开(公告)日：2018-05-03

申请号：US15674697

申请日：2017-08-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： HEMANTH JAGANNATHAN ,  SHOGO MOCHIZUKI

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/167 ,  H01L21/02 ,  H01L21/306 ,  H01L29/66

CPC classification number: H01L29/7827 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/02598 ,  H01L21/30604 ,  H01L29/0847 ,  H01L29/167 ,  H01L29/66666 ,  H01L29/785

Abstract: Low temperature epitaxial silicon deposition for forming the top source or drain regions of VTFET structures. The methods generally include epitaxially growing a silicon layer with a dopant at a temperature less 500° C. on a first surface and an additional surface to form a single crystalline silicon on the first surface and a polysilicon or amorphous silicon on the additional surface. The epitaxially grown silicon layer is then exposed to an etchant include HCl and germane at a temperature less than 500° C. for a period of time effective to selectively remove the polysilicon/amorphous silicon on the additional surface and form a germanium diffused region on and in an outer surface of the single crystalline silicon formed on the first surface.

公开(公告)号：US20140061815A1

公开(公告)日：2014-03-06

申请号：US14073366

申请日：2013-11-06

Applicant: International Business Machines Corporation

Inventor： HEMANTH JAGANNATHAN ,  Sivananda Kanakasabapathy

IPC: H01L27/092 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L29/7845 ,  H01L29/785

Abstract: A non-planar semiconductor transistor device includes a substrate layer. Conductive channels extend between corresponding source and drain electrodes. A gate stack extending in a direction perpendicular to the conductive channels crosses over the plurality of conductive channels. The gate stack includes a dielectric layer running along the substrate and the plurality of conductive channels and arranged with a substantially uniform layer thickness, a work-function electrode layer covers the dielectric layer and is arranged with a substantially uniform layer thickness, and a metal layer, distinct from the work-function electrode layer, covers the work-function electrode layer and is arranged with a substantially uniform height with respect to the substrate such that the metal layer fills a gap between proximate conductive channels of the plurality of conductive channels.

Abstract translation: 非平面半导体晶体管器件包括衬底层。 导电通道在相应的源极和漏极之间延伸。 沿垂直于导电通道的方向延伸的栅极堆叠跨过多个导电沟道。 栅极堆叠包括沿着衬底和多个导电沟道延伸并且布置成基本均匀的层厚度的电介质层，功函电极层覆盖电介质层并且布置成基本上均匀的层厚度，并且金属层 与工作功能电极层不同的是覆盖功函电极层，并且相对于衬底布置有基本均匀的高度，使得金属层填充多个导电沟道的邻近导电沟道之间的间隙。