公开(公告)号：US20230369492A1

公开(公告)日：2023-11-16

申请号：US18348579

申请日：2023-07-07

Applicant: International Business Machines Corporation

Inventor： INDIRA SESHADRI ,  ARDASHEIR RAHMAN ,  RUILONG XIE ,  HEMANTH JAGANNATHAN

IPC: H01L29/78 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L21/823821 ,  H01L29/6656 ,  H01L29/66795

Abstract: A method of forming a transistor structure is provided. The method includes forming on a substrate first and second mandrels for forming two-dimensional (2D) transistor fin elements defining a pitch gap region, depositing and anisotropically etching back the first spacer material to form first and second spacers in and around the first and second mandrels, respectively, conformally depositing and anisotropically etching back second spacer material around the first and second spacers and in the pitch gap region to define space for forming an odd number of one-dimensional (1D) transistor fin elements in the pitch gap region and depositing and anisotropically etching back the first spacer material in the space with enough cycles to fill the space to form a third spacer.

公开(公告)号：US20180204839A1

公开(公告)日：2018-07-19

申请号：US15406985

申请日：2017-01-16

Applicant: International Business Machines Corporation

Inventor： RUQIANG BAO ,  HEMANTH JAGANNATHAN ,  PAUL JAMISON ,  CHOONGHYUN LEE ,  VIJAY NARAYANAN

IPC: H01L27/092 ,  H01L29/49 ,  H01L21/8234 ,  H01L29/51

CPC classification number: H01L27/0924 ,  H01L21/823431 ,  H01L21/823437 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66666 ,  H01L29/7827

Abstract: A semiconductor device is provided and has an n-channel field effect transistor (nFET) bottom junction and a p-channel field effect transistor (pFET) bottom junction. The semiconductor device includes first and second fin formations operably disposed in the nFET and pFET bottom junctions, respectively. The semiconductor device can also include an nFET metal gate layer deposited for oxygen absorption onto a high-k dielectric layer provided about the first fin formation in the nFET bottom junction and onto a pFET metal gate layer provided about the second fin formation in the pFET bottom junction. Alternatively, the semiconductor device can include an oxygen scavenging layer deposited onto the pFET metal gate layer about the second fin formation in the pFET bottom junction and, with the pFET metal gate layer deposited onto the nFET metal gate layer about the first fin formation in the nFET bottom junction, onto the pFET metal gate layer in the nFET bottom junction.

公开(公告)号：US20190181051A1

公开(公告)日：2019-06-13

申请号：US16267479

申请日：2019-02-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Brent A. Anderson ,  RUQIANG BAO ,  Kangguo Cheng ,  HEMANTH JAGANNATHAN ,  CHOONGHYUN LEE ,  JUNLI WANG

IPC: H01L21/8238 ,  H01L29/08 ,  H01L29/06 ,  H01L29/78 ,  H01L21/28 ,  H01L29/49 ,  H01L23/535

Abstract: Forming a PFET work function metal layer on a p-type field effect transistor (PFET) fin in a PFET region and on an n-type field effect transistor (NFET) fin in an NFET region, removing a portion of the PFET work function metal layer between the PFET fin and the NFET fin, thinning the PFET work function metal layer, patterning an organic planarization layer on the PFET work function metal layer, where the organic planarization layer covers the PFET region and partially covers the NFET region, removing the PFET work function metal layer in the NFET region, by etching isotropically selective to the organic planarization layer and an insulator in the NFET region, removing the organic planarization layer, and conformally forming an NFET work function metal layer on the semiconductor structure.

公开(公告)号：US20190189774A1

公开(公告)日：2019-06-20

申请号：US16280100

申请日：2019-02-20

Applicant: International Business Machines Corporation

Inventor： RUQIANG BAO ,  HEMANTH JAGANNATHAN ,  CHOONGHYUN LEE ,  SHOGO MOCHIZUKI

IPC: H01L29/66 ,  H01L21/8238 ,  H01L21/02 ,  H01L27/092 ,  H01L29/786 ,  H01L29/423 ,  H01L29/06

CPC classification number: H01L29/66553 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/02175 ,  H01L21/02255 ,  H01L21/02321 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/02532 ,  H01L21/823814 ,  H01L21/823864 ,  H01L21/823885 ,  H01L27/092 ,  H01L29/0653 ,  H01L29/42392 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/78618 ,  H01L29/78642

Abstract: A method of fabricating a semiconductor device includes forming a fin on a substrate. Source/drain regions are arranged on the substrate on opposing sides of the fin. The method includes depositing a semiconductor layer on the source/drain regions. The method includes depositing a germanium containing layer on the fin and the semiconductor layer. The method further includes applying an anneal operation configured to chemically react the semiconductor layer with the germanium containing layer and form a silicon oxide layer.

公开(公告)号：US20170077256A1

公开(公告)日：2017-03-16

申请号：US14852459

申请日：2015-09-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： PRANEET ADUSUMILLI ,  HEMANTH JAGANNATHAN ,  ALEXANDER REZNICEK ,  OSCAR VAN DER STRATEN ,  CHIH-CHAO YANG

IPC: H01L29/49 ,  H01L29/66 ,  H01L27/088 ,  H01L23/528 ,  H01L23/532 ,  H01L21/28 ,  H01L29/40 ,  H01L21/768

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76877 ,  H01L21/76883 ,  H01L21/76897 ,  H01L21/823828 ,  H01L23/528 ,  H01L23/53209 ,  H01L27/088 ,  H01L29/401 ,  H01L29/66545 ,  H01L29/6656

Abstract: A CMOS fabrication process provides metal gates and contact metallization protected by metal cap layers resistant to reagents employed in downstream processing. Cobalt gates and contact metallization are accordingly feasible in CMOS processing requiring downstream wet cleans and etch processes that would otherwise compromise or destroy them. Low resistivity metal cap materials can be employed.

Abstract translation: CMOS制造工艺提供金属栅极和接触金属化，其被金属盖层保护，对下游处理中使用的试剂具有抗性。 因此，钴栅极和接触金属化在CMOS加工中是可行的，需要下游的湿法清洗和蚀刻工艺，否则会损害或破坏它们。 可以采用低电阻金属帽材料。

公开(公告)号：US20230101235A1

公开(公告)日：2023-03-30

申请号：US17486911

申请日：2021-09-28

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Ardasheir Rahman ,  HEMANTH JAGANNATHAN ,  Robert ROBISON ,  Brent Anderson ,  Heng Wu

IPC: H01L29/10 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L21/76 ,  H01L29/08

Abstract: A long channel field-effect transistor is incorporated in a semiconductor structure. A semiconductor fin forming a channel region is configured as a loop having an opening therein. A dielectric isolation region is within the opening. Source/drain regions epitaxially grown on fin end portions within the opening are electrically isolated by the isolation region. The source/drain regions, the isolation region and the channel are arranged as a closed loop. The semiconductor structure may further include a short channel, vertical transport field-effect transistor.

公开(公告)号：US20190319114A1

公开(公告)日：2019-10-17

申请号：US16454587

申请日：2019-06-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： RUQIANG BAO ,  HEMANTH JAGANNATHAN ,  CHOONGHYUN LEE ,  SHOGO MOCHIZUKI

IPC: H01L29/66 ,  H01L21/8238 ,  H01L21/02 ,  H01L27/092 ,  H01L29/06 ,  H01L29/786 ,  H01L29/423 ,  H01L29/78

Abstract: A method of fabricating a semiconductor device includes forming a fin on a substrate. Source/drain regions are arranged on the substrate on opposing sides of the fin. The method includes depositing a semiconductor layer on the source/drain regions. The method includes depositing a germanium containing layer on the fin and the semiconductor layer. The method further includes applying an anneal operation configured to chemically react the semiconductor layer with the germanium containing layer and form a silicon oxide layer.

公开(公告)号：US20220367700A1

公开(公告)日：2022-11-17

申请号：US17316832

申请日：2021-05-11

Applicant: International Business Machines Corporation

Inventor： INDIRA SESHADRI ,  ARDASHEIR RAHMAN ,  RUILONG XIE ,  HEMANTH JAGANNATHAN

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/8238

Abstract: A method of forming a transistor structure is provided. The method includes forming on a substrate first and second mandrels for forming two-dimensional (2D) transistor fin elements defining a pitch gap region, depositing and anisotropically etching back the first spacer material to form first and second spacers in and around the first and second mandrels, respectively, conformally depositing and anisotropically etching back second spacer material around the first and second spacers and in the pitch gap region to define space for forming an odd number of one-dimensional (1D) transistor fin elements in the pitch gap region and depositing and anisotropically etching back the first spacer material in the space with enough cycles to fill the space to form a third spacer.

公开(公告)号：US20200295147A1

公开(公告)日：2020-09-17

申请号：US16351729

申请日：2019-03-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： RUQIANG BAO ,  HEMANTH JAGANNATHAN ,  Paul Charles Jamison ,  Choonghyun Lee ,  Sanjay C. Mehta ,  Vijay Narayanan

IPC: H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/778

Abstract: A technique relates to a semiconductor device. A gate stack is formed on a fin, the gate stack being formed to have a length in a vertical direction. A gate contact is formed adjacent to the gate stack for the length of the gate stack in the vertical direction.

公开(公告)号：US20190198500A1

公开(公告)日：2019-06-27

申请号：US16293853

申请日：2019-03-06

Applicant: International Business Machines Corporation

Inventor： RUQIANG BAO ,  HEMANTH JAGANNATHAN ,  PAUL JAMISON ,  CHOONGHYUN LEE ,  VIJAY NARAYANAN

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/8234

CPC classification number: H01L27/0924 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/823885 ,  H01L27/092 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66666 ,  H01L29/7827

Abstract: A semiconductor device is provided and has an n-channel field effect transistor (nFET) bottom junction and a p-channel field effect transistor (pFET) bottom junction. The semiconductor device includes first and second fin formations operably disposed in the nFET and pFET bottom junctions, respectively. The semiconductor device can also include an nFET metal gate layer deposited for oxygen absorption onto a high-k dielectric layer provided about the first fin formation in the nFET bottom junction and onto a pFET metal gate layer provided about the second fin formation in the pFET bottom junction. Alternatively, the semiconductor device can include an oxygen scavenging layer deposited onto the pFET metal gate layer about the second fin formation in the pFET bottom junction and, with the pFET metal gate layer deposited onto the nFET metal gate layer about the first fin formation in the nFET bottom junction, onto the pFET metal gate layer in the nFET bottom junction.