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1.发明申请公开(公告)号：US20190214311A1
公开(公告)日：2019-07-11
申请号：US16241677
申请日：2019-01-07
发明人： Indira Seshadri , Ekmini Anuja De Silva , Jing Guo , Romain J. Lallement , Ruqiang Bao , Zhenxing Bi , Sivananda Kanakasabapathy
IPC分类号： H01L21/8238 , H01L21/28 , H01L27/092 , H01L21/308
CPC分类号： H01L21/823842 , H01L21/28185 , H01L21/3081 , H01L21/8221 , H01L21/823821 , H01L27/0688 , H01L27/0924 , H01L29/0673 , H01L29/42392 , H01L29/6653 , H01L29/66553 , H01L29/6681 , H01L29/7853
摘要： A semiconductor structure comprises a semiconductor substrate, an N-type stacked nanosheet channel structure formed on the semiconductor substrate, and a P-type stacked nanosheet channel structure formed adjacent to the N-type stacked nanosheet channel structure on the semiconductor substrate. Each of the adjacent N-type and P-type stacked nanosheet channel structures comprises a plurality of stacked channel regions with each such channel region being substantially surrounded by a gate dielectric layer and a gate work function metal layer, and with the gate work function metal layer being separated from the channel regions by the gate dielectric layer. The gate dielectric and gate work function metal layers of the adjacent N-type and P-type stacked nanosheet channel structures are substantially eliminated from a shared gate region between the adjacent N-type and P-type stacked nanosheet channel structures.
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公开(公告)号：US10083964B1
公开(公告)日：2018-09-25
申请号：US15812249
申请日：2017-11-14
IPC分类号： H01L27/092 , H01L29/06 , H01L21/3065 , H01L21/225 , H01L21/02 , H01L21/762 , H01L21/8238 , H01L29/66 , H01L21/308
摘要： A double diffusion break (DDB) gate structure is provided by removing the vestigial antenna to provide a space and the space is filled, at least in part, with an interlevel dielectric (ILD) material. Removal of the vestigial antenna from the DDB gate structure will reduce the device capacitance and improve device performance, while enabling DDB in tight integration schemes.
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公开(公告)号：US10115724B1
公开(公告)日：2018-10-30
申请号：US15634799
申请日：2017-06-27
IPC分类号： H01L27/092 , H01L29/06 , H01L21/3065 , H01L21/225 , H01L21/02 , H01L21/762 , H01L21/8238 , H01L29/66 , H01L21/308
摘要： A double diffusion break (DDB) gate structure is provided by removing the vestigial antenna to provide a space and the space is filled, at least in part, with an interlevel dielectric (ILD) material. Removal of the vestigial antenna from the DDB gate structure will reduce the device capacitance and improve device performance, while enabling DDB in tight integration schemes.
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公开(公告)号：US09431399B1
公开(公告)日：2016-08-30
申请号：US14969533
申请日：2015-12-15
发明人： Emre Alptekin , Balasubramanian Pranatharthiharan , Sivananda Kanakasabapathy , Ravikumar Ramachandran , Mickey H. Yu
IPC分类号： H01L21/336 , H01L27/092 , H01L21/8238 , H01L29/66
CPC分类号： H01L27/0924 , H01L21/823814 , H01L21/823821 , H01L21/823871 , H01L29/66545
摘要： A method for forming a semiconductor device comprises forming a first fin and a second fin on a semiconductor substrate, forming a sacrificial gate stack over a channel region of the first fin and the second fin, depositing a layer of spacer material over the first fin and the second fin, depositing a layer of dielectric material over the layer of spacer material, removing a portion of the dielectric material to form a first cavity that exposes a portion of the first fin, epitaxially growing a first semiconductor material on the exposed portion of the first fin to form a source/drain region on the first fin, depositing a protective layer on the source/drain region on the first fin, removing a portion of the dielectric material to form a second cavity that exposes a portion of the second fin, and epitaxially growing a source/drain region on the second fin.
摘要翻译： 一种用于形成半导体器件的方法包括在半导体衬底上形成第一鳍片和第二鳍片，在第一鳍片和第二鳍片的沟道区域上形成牺牲栅叠层，在第一鳍片之上沉积间隔物材料层， 第二鳍片，在隔离层材料层上沉积介电材料层，去除电介质材料的一部分以形成暴露第一鳍片的一部分的第一腔体，在第一鳍片的暴露部分上外延生长第一半导体材料 第一鳍片，以在第一鳍片上形成源极/漏极区域，在第一鳍片上的源极/漏极区域上沉积保护层，去除电介质材料的一部分以形成暴露第二鳍片的一部分的第二腔体， 并在第二鳍片上外延生长源/漏区域。
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5.发明授权High performance non-planar semiconductor devices with metal filled inter-fin gaps 有权具有金属填充的间隙间隙的高性能非平面半导体器件公开(公告)号：US08901667B2
公开(公告)日：2014-12-02
申请号：US14073366
申请日：2013-11-06
IPC分类号： H01L29/76 , H01L29/78 , H01L27/092
CPC分类号： H01L27/0924 , H01L29/7845 , H01L29/785
摘要： A non-planar semiconductor transistor device includes a substrate layer. Conductive channels extend between corresponding source and drain electrodes. A gate stack extending in a direction perpendicular to the conductive channels crosses over the plurality of conductive channels. The gate stack includes a dielectric layer running along the substrate and the plurality of conductive channels and arranged with a substantially uniform layer thickness, a work-function electrode layer covers the dielectric layer and is arranged with a substantially uniform layer thickness, and a metal layer, distinct from the work-function electrode layer, covers the work-function electrode layer and is arranged with a substantially uniform height with respect to the substrate such that the metal layer fills a gap between proximate conductive channels of the plurality of conductive channels.
摘要翻译： 非平面半导体晶体管器件包括衬底层。 导电通道在相应的源极和漏极之间延伸。 沿垂直于导电通道的方向延伸的栅极堆叠跨过多个导电沟道。 栅极堆叠包括沿着衬底和多个导电沟道延伸并且布置成基本均匀的层厚度的电介质层，功函电极层覆盖电介质层并且布置成基本上均匀的层厚度，并且金属层 与工作功能电极层不同的是覆盖功函电极层，并且相对于衬底布置有基本均匀的高度，使得金属层填充多个导电沟道的邻近导电沟道之间的间隙。
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6.发明申请HIGH PERFORMANCE NON-PLANAR SEMICONDUCTOR DEVICES WITH METAL FILLED INTER-FIN GAPS 有权高性能非平面半导体器件，带金属填充金属间隙公开(公告)号：US20140061815A1
公开(公告)日：2014-03-06
申请号：US14073366
申请日：2013-11-06
IPC分类号： H01L27/092 , H01L29/78
CPC分类号： H01L27/0924 , H01L29/7845 , H01L29/785
摘要： A non-planar semiconductor transistor device includes a substrate layer. Conductive channels extend between corresponding source and drain electrodes. A gate stack extending in a direction perpendicular to the conductive channels crosses over the plurality of conductive channels. The gate stack includes a dielectric layer running along the substrate and the plurality of conductive channels and arranged with a substantially uniform layer thickness, a work-function electrode layer covers the dielectric layer and is arranged with a substantially uniform layer thickness, and a metal layer, distinct from the work-function electrode layer, covers the work-function electrode layer and is arranged with a substantially uniform height with respect to the substrate such that the metal layer fills a gap between proximate conductive channels of the plurality of conductive channels.
摘要翻译： 非平面半导体晶体管器件包括衬底层。 导电通道在相应的源极和漏极之间延伸。 沿垂直于导电通道的方向延伸的栅极堆叠跨过多个导电沟道。 栅极堆叠包括沿着衬底和多个导电沟道延伸并且布置成基本均匀的层厚度的电介质层，功函电极层覆盖电介质层并且布置成基本上均匀的层厚度，并且金属层 与工作功能电极层不同的是覆盖功函电极层，并且相对于衬底布置有基本均匀的高度，使得金属层填充多个导电沟道的邻近导电沟道之间的间隙。
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7.发明授权公开(公告)号：US10276452B1
公开(公告)日：2019-04-30
申请号：US15867834
申请日：2018-01-11
发明人： Indira Seshadri , Ekmini Anuja De Silva , Jing Guo , Romain J. Lallement , Ruqiang Bao , Zhenxing Bi , Sivananda Kanakasabapathy
IPC分类号： H01L21/8238 , H01L21/308 , H01L21/28 , H01L27/092 , H01L29/423 , H01L29/06 , H01L29/66 , H01L29/78
摘要： A method of forming a semiconductor structure includes forming first and second stacked nanosheet channel structures on a semiconductor substrate, with each nanosheet channel structure including a plurality of stacked channel regions interspersed with sacrificial regions. In a resulting semiconductor structure, an N-type stacked nanosheet channel structure is formed on the semiconductor substrate, and a P-type stacked nanosheet channel structure is formed adjacent to the N-type stacked nanosheet channel structure on the semiconductor substrate. Each of the adjacent N-type and P-type stacked nanosheet channel structures includes a plurality of stacked channel regions with each such channel region being substantially surrounded by a gate dielectric layer and a gate work function metal layer. The gate dielectric and gate work function metal layers of the adjacent N-type and P-type stacked nanosheet channel structures are substantially eliminated from a shared gate region between the adjacent N-type and P-type stacked nanosheet channel structures.
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