公开(公告)号：US10063243B2

公开(公告)日：2018-08-28

申请号：US15668790

申请日：2017-08-04

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jingdong Deng ,  Chung S. Ho ,  David Flye ,  Zhenrong Jin ,  Ramana M. Malladi

IPC: H03L7/06 ,  H03L7/087 ,  H03L7/099 ,  G06F17/50

CPC classification number: H03L7/087 ,  G06F17/5045 ,  H03L7/0991 ,  H03L7/0995 ,  H03L7/0997 ,  H03L2207/06 ,  H03L2207/50 ,  H05K999/99

Abstract: A phase locked loop circuit is disclosed. The phase locked loop circuit includes a ring oscillator. The phase locked loop circuit also includes a digital path including a digital phase detector. The phase locked loop circuit further includes an analog path including a linear phase detector. Additionally, the phase locked loop circuit includes a feedback path connecting an output of the ring oscillator to an input of the digital path and an input of the analog path. The digital path and the analog path are parallel paths. The digital path provides a digital tuning signal the ring oscillator that digitally controls a frequency of the ring oscillator. The analog path provides an analog tuning signal the ring oscillator that continuously controls the frequency of the ring oscillator.

公开(公告)号：US10693471B2

公开(公告)日：2020-06-23

申请号：US16030970

申请日：2018-07-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jingdong Deng ,  Rupert Shiu Chung Ho ,  David Flye ,  Zhenrong Jin ,  Ramana M. Malladi

IPC: H03L7/087 ,  H03L7/099 ,  G06F30/30

Abstract: A phase locked loop circuit is disclosed. The phase locked loop circuit includes a ring oscillator. The phase locked loop circuit also includes a digital path including a digital phase detector. The phase locked loop circuit further includes an analog path including a linear phase detector. Additionally, the phase locked loop circuit includes a feedback path connecting an output of the ring oscillator to an input of the digital path and an input of the analog path. The digital path and the analog path are parallel paths. The digital path provides a digital tuning signal the ring oscillator that digitally controls a frequency of the ring oscillator. The analog path provides an analog tuning signal the ring oscillator that continuously controls the frequency of the ring oscillator.

公开(公告)号：US10686452B2

公开(公告)日：2020-06-16

申请号：US16013236

申请日：2018-06-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jingdong Deng ,  Rupert Shiu Chung Ho ,  David Flye ,  Zhenrong Jin ,  Ramana M. Malladi

IPC: H03L7/087 ,  H03L7/099 ,  G06F30/30

Abstract: A phase locked loop circuit is disclosed. The phase locked loop circuit includes a ring oscillator. The phase locked loop circuit also includes a digital path including a digital phase detector. The phase locked loop circuit further includes an analog path including a linear phase detector. Additionally, the phase locked loop circuit includes a feedback path connecting an output of the ring oscillator to an input of the digital path and an input of the analog path. The digital path and the analog path are parallel paths. The digital path provides a digital tuning signal the ring oscillator that digitally controls a frequency of the ring oscillator. The analog path provides an analog tuning signal the ring oscillator that continuously controls the frequency of the ring oscillator.

公开(公告)号：US09917591B2

公开(公告)日：2018-03-13

申请号：US15248792

申请日：2016-08-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jingdong Deng ,  Chung S. Ho ,  David Flye ,  Zhenrong Jin ,  Ramana M. Malladi

IPC: H03L7/06 ,  H03L7/087 ,  H03L7/099 ,  G06F17/50

CPC classification number: H03L7/087 ,  G06F17/5045 ,  H03L7/0991 ,  H03L7/0995 ,  H03L7/0997 ,  H03L2207/06 ,  H03L2207/50

Abstract: A phase locked loop circuit is disclosed. The phase locked loop circuit includes a ring oscillator. The phase locked loop circuit also includes a digital path including a digital phase detector. The phase locked loop circuit further includes an analog path including a linear phase detector. Additionally, the phase locked loop circuit includes a feedback path connecting an output of the ring oscillator to an input of the digital path and an input of the analog path. The digital path and the analog path are parallel paths. The digital path provides a digital tuning signal the ring oscillator that digitally controls a frequency of the ring oscillator. The analog path provides an analog tuning signal the ring oscillator that continuously controls the frequency of the ring oscillator.

公开(公告)号：US09906228B2

公开(公告)日：2018-02-27

申请号：US15248800

申请日：2016-08-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jingdong Deng ,  Chung S. Ho ,  David Flye ,  Zhenrong Jin ,  Ramana M. Malladi

IPC: H03L7/06 ,  H03L7/087 ,  H03L7/099 ,  G06F17/50

CPC classification number: H03L7/087 ,  G06F17/5045 ,  H03L7/0991 ,  H03L7/0995 ,  H03L7/0997 ,  H03L2207/06 ,  H03L2207/50

Abstract: A phase locked loop circuit is disclosed. The phase locked loop circuit includes a ring oscillator. The phase locked loop circuit also includes a digital path including a digital phase detector. The phase locked loop circuit further includes an analog path including a linear phase detector. Additionally, the phase locked loop circuit includes a feedback path connecting an output of the ring oscillator to an input of the digital path and an input of the analog path. The digital path and the analog path are parallel paths. The digital path provides a digital tuning signal the ring oscillator that digitally controls a frequency of the ring oscillator. The analog path provides an analog tuning signal the ring oscillator that continuously controls the frequency of the ring oscillator.

公开(公告)号：US09806723B2

公开(公告)日：2017-10-31

申请号：US15248822

申请日：2016-08-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jingdong Deng ,  Chung S. Ho ,  David Flye ,  Zhenrong Jin ,  Ramana M. Malladi

IPC: H03L7/06 ,  H03L7/087 ,  H03L7/099 ,  G06F17/50

CPC classification number: H03L7/087 ,  G06F17/5045 ,  H03L7/0991 ,  H03L7/0995 ,  H03L7/0997 ,  H03L2207/06 ,  H03L2207/50

Abstract: A phase locked loop circuit is disclosed. The phase locked loop circuit includes a ring oscillator. The phase locked loop circuit also includes a digital path including a digital phase detector. The phase locked loop circuit further includes an analog path including a linear phase detector. Additionally, the phase locked loop circuit includes a feedback path connecting an output of the ring oscillator to an input of the digital path and an input of the analog path. The digital path and the analog path are parallel paths. The digital path provides a digital tuning signal the ring oscillator that digitally controls a frequency of the ring oscillator. The analog path provides an analog tuning signal the ring oscillator that continuously controls the frequency of the ring oscillator.

公开(公告)号：US09252717B2

公开(公告)日：2016-02-02

申请号：US14295794

申请日：2014-06-04

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Anthony R. Bonaccio ,  Zhenrong Jin ,  Ram Kelkar ,  Anjali R. Malladi ,  Ramana M. Malladi

IPC: H03B5/08 ,  H03F1/26 ,  H03B5/12 ,  H03B5/10 ,  H03B5/34

CPC classification number: H03F1/26 ,  H03B5/10 ,  H03B5/1212 ,  H03B5/1225 ,  H03B5/1228 ,  H03B5/1243 ,  H03B5/34 ,  H03F3/301 ,  H03F3/45179 ,  H03F2200/372 ,  H03F2203/45562 ,  Y10T29/49119

Abstract: An approach for a transconductance cell for use in a voltage controlled oscillator (VCO) is provided. The transconductance cell includes a first NFET stack connected in series to a first PFET stack. The transconductance cell includes a second NFET stack connected in series to a second PFET stack. The first NFET stack and the first PFET stack are cross-coupled to the second NFET stack and the second PFET stack. The first NFET stack and the second NFET stack are connected to a tail node. The first PFET stack and the second PFET stack are connected to a power supply node.

Abstract translation: 提供了一种用于压控振荡器（VCO）的跨导单元的方法。 跨导单元包括与第一PFET堆叠串联连接的第一NFET堆叠。 跨导单元包括与第二PFET堆叠串联连接的第二NFET堆叠。 第一NFET堆叠和第一PFET堆叠交叉耦合到第二NFET堆叠和第二PFET堆叠。 第一个NFET堆叠和第二个NFET堆叠连接到一个尾部节点。 第一PFET堆叠和第二PFET堆叠连接到电源节点。