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公开(公告)号：US07718483B2
公开(公告)日：2010-05-18
申请号：US11399655
申请日：2006-04-07
IPC分类号： H01L21/8238
CPC分类号： H01L27/115 , H01L21/76229 , H01L27/1052 , H01L27/11521
摘要： In a method for manufacturing a non-volatile semiconductor device according to this invention, steps are provided for forming a plurality of first semiconductor portions over a substrate; selectively growing a plurality of second semiconductor portions in contacting with said plurality of first semiconductor portions respectively; partially removing said plurality of second semiconductor portions to prepare a plurality of floating gates with substantially flat surfaces; forming an insulating layer over said plurality of floating gates; and forming a control gate over said insulating layer.
摘要翻译： 在根据本发明的用于制造非易失性半导体器件的方法中，提供了用于在衬底上形成多个第一半导体部分的步骤; 选择性地生长与所述多个第一半导体部分接触的多个第二半导体部分; 部分地去除所述多个第二半导体部分以制备具有基本平坦表面的多个浮动栅极; 在所述多个浮动栅极上形成绝缘层; 以及在所述绝缘层上形成控制栅极。
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公开(公告)号：US20090011570A1
公开(公告)日：2009-01-08
申请号：US12146143
申请日：2008-06-25
申请人： Ichiro Mizushima , Yoshio Ozawa , Takashi Nakao , Akihito Yamamoto , Takashi Suzuki , Masahiro Kiyotoshi , Minako Inukai , Kaori Umezawa , Hiroaki Yamada
发明人： Ichiro Mizushima , Yoshio Ozawa , Takashi Nakao , Akihito Yamamoto , Takashi Suzuki , Masahiro Kiyotoshi , Minako Inukai , Kaori Umezawa , Hiroaki Yamada
IPC分类号： H01L21/76
CPC分类号： H01L21/764
摘要： A method of manufacturing a semiconductor device includes removing a part of a semiconductor substrate to form a protruding portion and a recess portion in a surface area of the semiconductor substrate, forming a first epitaxial semiconductor layer in the recess portion, forming a second epitaxial semiconductor layer on the protruding portion and the first epitaxial semiconductor layer, removing a first part of the second epitaxial semiconductor layer with a second part of the second epitaxial semiconductor layer left to expose a part of the first epitaxial semiconductor layer, and etching the first epitaxial semiconductor layer from the exposed part of the first epitaxial semiconductor layer to form a cavity under the second part of the second epitaxial semiconductor layer.
摘要翻译： 一种制造半导体器件的方法包括：去除半导体衬底的一部分以在半导体衬底的表面区域中形成突出部分和凹陷部分，在凹部中形成第一外延半导体层，形成第二外延半导体层 在所述突出部分和所述第一外延半导体层上，用所述第二外延半导体层的第二部分去除所述第二外延半导体层的第一部分，以露出所述第一外延半导体层的一部分，并且蚀刻所述第一外延半导体层 从第一外延半导体层的暴露部分形成在第二外延半导体层的第二部分下面的空腔。
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公开(公告)号：US20060258076A1
公开(公告)日：2006-11-16
申请号：US11399655
申请日：2006-04-07
IPC分类号： H01L21/8238
CPC分类号： H01L27/115 , H01L21/76229 , H01L27/1052 , H01L27/11521
摘要： In a method for manufacturing a non-volatile semiconductor device according to this invention, steps are provided for forming a plurality of first semiconductor portions over a substrate; selectively growing a plurality of second semiconductor portions in contacting with said plurality of first semiconductor portions respectively; partially removing said plurality of second semiconductor portions to prepare a plurality of floating gates with substantially flat surfaces; forming an insulating layer over said plurality of floating gates; and forming a control gate over said insulating layer.
摘要翻译： 在根据本发明的用于制造非易失性半导体器件的方法中，提供了用于在衬底上形成多个第一半导体部分的步骤; 选择性地生长与所述多个第一半导体部分接触的多个第二半导体部分; 部分地去除所述多个第二半导体部分以制备具有基本平坦表面的多个浮动栅极; 在所述多个浮动栅极上形成绝缘层; 以及在所述绝缘层上形成控制栅极。
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公开(公告)号：US06927139B2
公开(公告)日：2005-08-09
申请号：US10717719
申请日：2003-11-21
IPC分类号： H01L21/8247 , H01L21/336 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11524
摘要： A semiconductor memory encompasses a memory cell matrix, which embraces device isolation films running along the column-direction, arranged alternatively between the cell columns; first conductive layers having top surfaces lower than the device isolation films; inter-electrode dielectrics arranged on the corresponding first conductive layers, the inter-electrode dielectric has a dielectric constant larger than that of silicon oxide; and second conductive layers running along the row-direction, each of the second conductive layers arranged on the inter-electrode dielectric and the device isolation films so that the second conductive layer can be shared by the memory cell transistors arranged along the row-direction belonging to different cell columns.
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公开(公告)号：US08114755B2
公开(公告)日：2012-02-14
申请号：US12146143
申请日：2008-06-25
申请人： Ichiro Mizushima , Yoshio Ozawa , Takashi Nakao , Akihito Yamamoto , Takashi Suzuki , Masahiro Kiyotoshi , Minako Inukai , Kaori Umezawa , Hiroaki Yamada
发明人： Ichiro Mizushima , Yoshio Ozawa , Takashi Nakao , Akihito Yamamoto , Takashi Suzuki , Masahiro Kiyotoshi , Minako Inukai , Kaori Umezawa , Hiroaki Yamada
IPC分类号： H01L21/76
CPC分类号： H01L21/764
摘要： A method of manufacturing a semiconductor device includes removing a part of a semiconductor substrate to form a protruding portion and a recess portion in a surface area of the semiconductor substrate, forming a first epitaxial semiconductor layer in the recess portion, forming a second epitaxial semiconductor layer on the protruding portion and the first epitaxial semiconductor layer, removing a first part of the second epitaxial semiconductor layer with a second part of the second epitaxial semiconductor layer left to expose a part of the first epitaxial semiconductor layer, and etching the first epitaxial semiconductor layer from the exposed part of the first epitaxial semiconductor layer to form a cavity under the second part of the second epitaxial semiconductor layer.
摘要翻译： 一种制造半导体器件的方法包括：去除半导体衬底的一部分以在半导体衬底的表面区域中形成突出部分和凹陷部分，在凹部中形成第一外延半导体层，形成第二外延半导体层 在所述突出部分和所述第一外延半导体层上，用所述第二外延半导体层的第二部分去除所述第二外延半导体层的第一部分，以露出所述第一外延半导体层的一部分，并且蚀刻所述第一外延半导体层 从第一外延半导体层的暴露部分形成在第二外延半导体层的第二部分下面的空腔。
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16.发明申请公开(公告)号：US20100171164A1
公开(公告)日：2010-07-08
申请号：US12659703
申请日：2010-03-17
申请人： Yoshio Ozawa , Ichiro Mizushima , Takashi Nakao , Akihito Yamamoto , Takashi Suzuki , Masahiro Kiyotoshi
发明人： Yoshio Ozawa , Ichiro Mizushima , Takashi Nakao , Akihito Yamamoto , Takashi Suzuki , Masahiro Kiyotoshi
IPC分类号： H01L27/115 , H01L29/788
CPC分类号： H01L27/115 , H01L21/84 , H01L27/11521 , H01L27/11524 , H01L27/1203
摘要： A nonvolatile semiconductor memory device including a semiconductor substrate having a semiconductor layer and an insulating material provided on a surface thereof, a surface of the insulating material is covered with the semiconductor layer, and a plurality of memory cells provided on the semiconductor layer, the memory cells includes a first dielectric film provided by covering the surface of the semiconductor layer, a plurality of charge storage layers provided above the insulating material and on the first dielectric film, a plurality of second dielectric films provided on the each charge storage layer, a plurality of conductive layers provided on the each second dielectric film, and an impurity diffusion layer formed partially or overall at least above the insulating material and inside the semiconductor layer and at least a portion of a bottom end thereof being provided by an upper surface of the insulating material.
摘要翻译： 一种非易失性半导体存储器件，包括具有半导体层和设置在其表面上的绝缘材料的半导体衬底，绝缘材料的表面被半导体层覆盖，并且设置在半导体层上的多个存储单元，存储器 电池包括通过覆盖半导体层的表面而提供的第一电介质膜，设置在绝缘材料上方和第一电介质膜上的多个电荷存储层，设置在每个电荷存储层上的多个第二电介质膜，多个 设置在每个第二电介质膜上的导电层，以及杂质扩散层，其部分或整体形成在绝缘材料的至少上方和半导体层的内部，并且其底端的至少一部分由绝缘体的上表面 材料。
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公开(公告)号：US07651930B2
公开(公告)日：2010-01-26
申请号：US12146802
申请日：2008-06-26
申请人： Takashi Suzuki , Hirokazu Ishida , Ichiro Mizushima , Yoshio Ozawa , Fumiki Aiso , Katsuyuki Sekine , Takashi Nakao , Yoshihiko Saito
发明人： Takashi Suzuki , Hirokazu Ishida , Ichiro Mizushima , Yoshio Ozawa , Fumiki Aiso , Katsuyuki Sekine , Takashi Nakao , Yoshihiko Saito
IPC分类号： H01L21/20
CPC分类号： H01L27/115 , H01L21/76264 , H01L21/84 , H01L27/11521 , H01L27/11524 , H01L27/1203 , H01L29/66825
摘要： A method of manufacturing a semiconductor storage device includes providing an opening portion in a plurality of positions in an insulating film formed on a silicon substrate, and thereafter forming an amorphous silicon film on the insulating film, in which the opening portions are formed, and in the opening portions. Then, trenches are formed to divide the amorphous silicon film, in the vicinity of a midpoint between adjacent opening portions, into a portion on one opening portion side and a portion on the other opening portion side. Next, the amorphous silicon film, in which the trenches are formed, is annealed and subjected to solid-phase crystallization to form a single crystal with the opening portions used as seeds, and thereby a silicon single-crystal layer is formed. Then, a memory cell array is formed on the silicon single-crystal layer.
摘要翻译： 一种制造半导体存储装置的方法包括在形成在硅衬底上的绝缘膜中的多个位置提供开口部分，然后在其中形成开口部分的绝缘膜上形成非晶硅膜，并且在 开口部。 然后，形成沟槽，将相邻的开口部之间的中点附近的非晶硅膜分割成一个开口部侧的一部分和另一个开口部侧的一部分。 接着，对其中形成沟槽的非晶硅膜进行退火并进行固相结晶以形成具有用作晶种的开口部分的单晶，从而形成硅单晶层。 然后，在硅单晶层上形成存储单元阵列。
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18.发明申请公开(公告)号：US20050003619A1
公开(公告)日：2005-01-06
申请号：US10717719
申请日：2003-11-21
IPC分类号： H01L21/8247 , H01L21/336 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11524
摘要： A semiconductor memory encompasses a memory cell matrix, which embraces device isolation films running along the column-direction, arranged alternatively between the cell columns; first conductive layers having top surfaces lower than the device isolation films; inter-electrode dielectrics arranged on the corresponding first conductive layers, the inter-electrode dielectric has a dielectric constant larger than that of silicon oxide; and second conductive layers running along the row-direction, each of the second conductive layers arranged on the inter-electrode dielectric and the device isolation films so that the second conductive layer can be shared by the memory cell transistors arranged along the row-direction belonging to different cell columns.
摘要翻译： 半导体存储器包括存储单元矩阵，其包括沿列方向延伸的器件隔离膜，交替地布置在单元列之间; 第一导电层的顶表面低于器件隔离膜; 布置在相应的第一导电层上的电极间电介质，所述电极间电介质的介电常数大于氧化硅的介电常数; 和沿着行方向延伸的第二导电层，每个第二导电层布置在电极间电介质和器件隔离膜上，使得第二导电层可以被沿着行方向归属布置的存储单元晶体管共享 到不同的细胞柱。
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公开(公告)号：US08637915B2
公开(公告)日：2014-01-28
申请号：US13007258
申请日：2011-01-14
申请人： Masayuki Ichige , Fumitaka Arai , Riichiro Shirota , Toshitake Yaegashi , Yoshio Ozawa , Akihito Yamamoto , Ichiro Mizushima , Yoshihiko Saito
发明人： Masayuki Ichige , Fumitaka Arai , Riichiro Shirota , Toshitake Yaegashi , Yoshio Ozawa , Akihito Yamamoto , Ichiro Mizushima , Yoshihiko Saito
IPC分类号： H01L29/788
CPC分类号： H01L29/42336 , H01L21/28273 , H01L27/0207 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/42324 , H01L29/7881
摘要： A nonvolatile semiconductor memory includes first and second memory cells having a floating gate and a control gate. The floating gate of the first and second memory cells is comprised a first part, and a second part arranged on the first part, and a width of the second part in an extending direction of the control gate is narrower than that of the first part. A first space between the first parts of the first and second memory cells is filled with one kind of an insulator. The control gate is arranged at a second space between the second parts of the first and second memory cells.
摘要翻译： 非易失性半导体存储器包括具有浮动栅极和控制栅极的第一和第二存储单元。 第一和第二存储单元的浮动栅极包括第一部分和布置在第一部分上的第二部分，并且第二部分在控制栅极的延伸方向上的宽度比第一部分的宽度窄。 第一和第二存储单元的第一部分之间的第一空间填充有一种绝缘体。 控制栅极被布置在第一和第二存储单元的第二部分之间的第二空间处。
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公开(公告)号：US08324679B2
公开(公告)日：2012-12-04
申请号：US13430153
申请日：2012-03-26
申请人： Masayuki Ichige , Fumitaka Arai , Riichiro Shirota , Toshitake Yaegashi , Yoshio Ozawa , Akihito Yamamoto , Ichiro Mizushima , Yoshihiko Saito
发明人： Masayuki Ichige , Fumitaka Arai , Riichiro Shirota , Toshitake Yaegashi , Yoshio Ozawa , Akihito Yamamoto , Ichiro Mizushima , Yoshihiko Saito
IPC分类号： H01L29/788
CPC分类号： H01L29/42336 , H01L21/28273 , H01L27/0207 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/42324 , H01L29/7881
摘要： A nonvolatile semiconductor memory includes first and second memory cells having a floating gate and a control gate. The floating gate of the first and second memory cells is comprised a first part, and a second part arranged on the first part, and a width of the second part in an extending direction of the control gate is narrower than that of the first part. A first space between the first parts of the first and second memory cells is filled with one kind of an insulator. The control gate is arranged at a second space between the second parts of the first and second memory cells.
摘要翻译： 非易失性半导体存储器包括具有浮动栅极和控制栅极的第一和第二存储单元。 第一和第二存储单元的浮动栅极包括第一部分和布置在第一部分上的第二部分，并且第二部分在控制栅极的延伸方向上的宽度比第一部分的宽度窄。 第一和第二存储单元的第一部分之间的第一空间填充有一种绝缘体。 控制栅极被布置在第一和第二存储单元的第二部分之间的第二空间处。
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