利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

115 条记录 (耗时 0.04 秒)

    Non-volatile semiconductor memory device
    9.
    发明申请
    Non-volatile semiconductor memory device 失效
    非易失性半导体存储器件

    公开(公告)号：US20050047210A1

    公开(公告)日：2005-03-03

    申请号：US10965775

    申请日：2004-10-18

    申请人： Yasuhiko Matsunaga ,  Toshitake Yaegashi ,  Fumitaka Arai ,  Riichiro Shirota

    发明人： Yasuhiko Matsunaga ,  Toshitake Yaegashi ,  Fumitaka Arai ,  Riichiro Shirota

    IPC分类号： G11C16/02 ,  G11C16/04 ,  G11C16/06 ,  G11C16/10 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C11/34

    CPC分类号： G11C16/0483 ,  G11C16/10

    摘要： A non-volatile semiconductor memory device having a write mode in which wrong writing is prevented surely. The storage device comprises a NAND cell comprising a plurality of memory transistors connected in series and also connected at one end via a select gate transistor CG1 to a bit line BL and at the other end via a select gate transistor SG2 to a common source line SL. A write voltage Vpgm is applied to a control gate of a selected memory transistor in the NAND cell and Vss is applied to the controls gates of non-select memory transistors each adjacent to the selected memory transistor to thereby write data into the select memory transistor. When a second memory transistor from the bitline BL side is selected in the writing operation, a medium voltage Vpass is applied to the control gate of a first non-selected memory transistor from the bit line BL side, and a medium voltage Vpass is applied to the control gates of third and subsequent non-selected memory transistors from the bit line BL side.

    摘要翻译： 具有写入模式的非易失性半导体存储器件，其中可以可靠地防止写入错误。 存储装置包括NAND单元，其包括串联连接的多个存储晶体管，并且一端经选择栅极晶体管CG1连接到位线BL，另一端经由选择栅极晶体管SG2连接到公共源极线SL 。 写入电压Vpgm被施加到NAND单元中所选择的存储晶体管的控制栅极，并且Vss被施加到与选择的存储晶体管相邻的非选择存储晶体管的控制栅极，从而将数据写入选择存储晶体管。 当在写入操作中选择来自位线BL侧的第二存储晶体管时，从位线BL侧向第一非选择存储晶体管的控制栅极施加中等电压Vpass，并将中压Vpass施加到 来自位线BL侧的第三和随后的未选择的存储器晶体管的控制栅极。

    Non-volatile semiconductor memory device
    10.
    发明授权
    Non-volatile semiconductor memory device 失效
    非易失性半导体存储器件

    公开(公告)号：US07184309B2

    公开(公告)日：2007-02-27

    申请号：US10965775

    申请日：2004-10-18

    申请人： Yasuhiko Matsunaga ,  Toshitake Yaegashi ,  Fumitaka Arai ,  Riichiro Shirota

    发明人： Yasuhiko Matsunaga ,  Toshitake Yaegashi ,  Fumitaka Arai ,  Riichiro Shirota

    IPC分类号： G11C16/04

    CPC分类号： G11C16/0483 ,  G11C16/10

    摘要： A non-volatile semiconductor memory device having a write mode in which wrong writing is prevented surely. The storage device comprises a NAND cell comprising a plurality of memory transistors connected in series and also connected at one end via a select gate transistor CG1 to a bit line BL and at the other end via a select gate transistor SG2 to a common source line SL. A write voltage Vpgm is applied to a control gate of a selected memory transistor in the NAND cell and Vss is applied to the controls gates of non-select memory transistors each adjacent to the selected memory transistor to thereby write data into the select memory transistor. When a second memory transistor from the bitline BL side is selected in the writing operation, a medium voltage Vpass is applied to the control gate of a first non-selected memory transistor from the bit line BL side, and a medium voltage Vpass is applied to the control gates of third and subsequent non-selected memory transistors from the bit line BL side.

    摘要翻译： 具有写入模式的非易失性半导体存储器件，其中可以可靠地防止写入错误。 存储装置包括NAND单元，其包括串联连接的多个存储晶体管，并且其一端经由选择栅极晶体管CG 1连接到位线BL，另一端经由选择栅极晶体管SG2连接到公共源极 线SL。 写入电压Vpgm被施加到NAND单元中所选择的存储晶体管的控制栅极，并且Vss被施加到与选择的存储晶体管相邻的非选择存储晶体管的控制栅极，从而将数据写入选择存储晶体管。 当在写入操作中选择来自位线BL侧的第二存储晶体管时，从位线BL侧向第一非选择存储晶体管的控制栅极施加中等电压Vpass，并将中压Vpass施加到 来自位线BL侧的第三和随后的未选择的存储器晶体管的控制栅极。