公开(公告)号：US20110101417A1

公开(公告)日：2011-05-05

申请号：US13005589

申请日：2011-01-13

申请人： Tsuneo OGURA ,  Masakazu Yamaguchi ,  Tomoki Inoue ,  Hideaki Ninomiya ,  Koichi Sugiyama

发明人： Tsuneo OGURA ,  Masakazu Yamaguchi ,  Tomoki Inoue ,  Hideaki Ninomiya ,  Koichi Sugiyama

IPC分类号： H01L29/739

CPC分类号： H01L29/1095 ,  H01L29/0834 ,  H01L29/7397

摘要： A semiconductor device comprises a first base layer of a first conductivity type; a plurality of second base layers of a second conductivity type, provided on a part of a first surface of the first base layer; trenches formed on each side of the second base layers, and formed to be deeper than the second base layers; an emitter layer formed along the trench on a surface of the second base layers; a collector layer of the second conductivity type, provided on a second surface of the first base layer opposite to the first surface; an insulating film formed on an inner wall of the trench, the insulating film being thicker on a bottom of the trench than on a side surface of the trench; a gate electrode formed within the trench, and isolated from the second base layers and the emitter layer by the insulating film; and a space section provided between the second base layers adjacent to each other, the space section being deeper than the second base layers and being electrically isolated from the emitter layer and the second base layers.

摘要翻译： 半导体器件包括第一导电类型的第一基极层; 多个第二导电类型的第二基层，设置在所述第一基底层的第一表面的一部分上; 沟槽形成在第二基底层的每一侧上，并且形成为比第二基底层更深; 在所述第二基底层的表面上沿着所述沟槽形成的发射极层; 设置在与第一表面相对的第一基底层的第二表面上的第二导电类型的集电极层; 形成在所述沟槽的内壁上的绝缘膜，所述绝缘膜在所述沟槽的底部比在所述沟槽的侧表面上更厚; 形成在所述沟槽内并与所述第二基极层和所述发射极层通过所述绝缘膜隔离的栅电极; 以及设置在彼此相邻的第二基底层之间的空间部分，空间部分比第二基底层更深，并且与发射极层和第二基底层电隔离。

公开(公告)号：US07781869B2

公开(公告)日：2010-08-24

申请号：US11498793

申请日：2006-08-04

申请人： Tomoki Inoue ,  Koichi Sugiyama ,  Hideaki Ninomiya ,  Tsuneo Ogura

发明人： Tomoki Inoue ,  Koichi Sugiyama ,  Hideaki Ninomiya ,  Tsuneo Ogura

IPC分类号： H01L31/075 ,  H01L27/095

CPC分类号： H01L29/868 ,  H01L29/0623 ,  H01L29/861 ,  H01L29/872 ,  H01L29/8725

摘要： A semiconductor device including a base layer of a first conductivity type having a first main surface and a second main surface opposite the first main surface, a first main electrode layer connected to the first main surface, control regions arranged inside grooves penetrating the first main electrode layer and reach inside the base layer, and a second main electrode layer of the first conductivity type and connected to the second main surface.

摘要翻译： 一种半导体器件，包括具有第一主表面和与第一主表面相对的第二主表面的第一导电类型的基底层，连接到第一主表面的第一主电极层，布置在穿过第一主电极的沟槽内的控制区域 并且到达基底层内部，并且具有第一导电类型并连接到第二主表面的第二主电极层。

公开(公告)号：US20060267129A1

公开(公告)日：2006-11-30

申请号：US11498793

申请日：2006-08-04

申请人： Tomoki Inoue ,  Koichi Sugiyama ,  Hideaki Ninomiya ,  Tsuneo Ogura

发明人： Tomoki Inoue ,  Koichi Sugiyama ,  Hideaki Ninomiya ,  Tsuneo Ogura

IPC分类号： H01L31/07

CPC分类号： H01L29/868 ,  H01L29/0623 ,  H01L29/861 ,  H01L29/872 ,  H01L29/8725

摘要： A semiconductor device including a base layer of a first conductivity type having a first main surface and a second main surface opposite the first main surface, a first main electrode layer connected to the first main surface, control regions arranged inside grooves penetrating the first main electrode layer and reach inside the base layer, and a second main electrode layer of the first conductivity type and connected to the second main surface.

摘要翻译： 一种半导体器件，包括具有第一主表面和与第一主表面相对的第二主表面的第一导电类型的基底层，连接到第一主表面的第一主电极层，布置在穿过第一主电极的沟槽内的控制区域 并且到达基底层内部，并且具有第一导电类型并连接到第二主表面的第二主电极层。

公开(公告)号：US06566691B1

公开(公告)日：2003-05-20

申请号：US09672963

申请日：2000-09-29

申请人： Tomoki Inoue ,  Koichi Sugiyama ,  Hideaki Ninomiya ,  Tsuneo Ogura

发明人： Tomoki Inoue ,  Koichi Sugiyama ,  Hideaki Ninomiya ,  Tsuneo Ogura

IPC分类号： H01L2978

CPC分类号： H01L29/66348 ,  H01L29/7397

摘要： An IGBT has a p-emitter layer and p-base layer, which are arranged on both sides of an n-base layer. A pair of main trenches are formed to extend through the p-base layer and reach the n-base layer. In a current path region interposed between the main trenches, a pair of n-emitter layers are formed on the surface of the p-base layer. A narrowing trench is formed to extend through the p-base layer and reach the n-base layer. The narrowing trench narrows a hole flow path formed from the n-base layer to the emitter electrode through the p-base layer, thereby increasing the hole current resistance.

摘要翻译： IGBT具有布置在n基层的两侧的p发射极层和p基极层。 一对主沟槽形成为延伸穿过p基层并到达n基层。 在介于主沟槽之间的电流路径区域中，在p基层的表面上形成一对n - 发射极层。 形成窄沟以延伸穿过p基层并到达n基层。 窄沟槽通过p基层使从n基层形成的空穴流路变窄到发射极，从而增加空穴电流电阻。

公开(公告)号：US08319314B2

公开(公告)日：2012-11-27

申请号：US13005589

申请日：2011-01-13

申请人： Tsuneo Ogura ,  Masakazu Yamaguchi ,  Tomoki Inoue ,  Hideaki Ninomiya ,  Koichi Sugiyama

发明人： Tsuneo Ogura ,  Masakazu Yamaguchi ,  Tomoki Inoue ,  Hideaki Ninomiya ,  Koichi Sugiyama

IPC分类号： H01L29/739 ,  H01L27/082 ,  H01L29/00 ,  H01L21/02

CPC分类号： H01L29/1095 ,  H01L29/0834 ,  H01L29/7397

摘要： A semiconductor device comprises a first base layer of a first conductivity type; a plurality of second base layers of a second conductivity type, provided on a part of a first surface of the first base layer; trenches formed on each side of the second base layers, and formed to be deeper than the second base layers; an emitter layer formed along the trench on a surface of the second base layers; a collector layer of the second conductivity type, provided on a second surface of the first base layer opposite to the first surface; an insulating film formed on an inner wall of the trench, the insulating film being thicker on a bottom of the trench than on a side surface of the trench; a gate electrode formed within the trench, and isolated from the second base layers and the emitter layer by the insulating film; and a space section provided between the second base layers adjacent to each other, the space section being deeper than the second base layers and being electrically isolated from the emitter layer and the second base layers.

摘要翻译： 半导体器件包括第一导电类型的第一基极层; 多个第二导电类型的第二基层，设置在所述第一基底层的第一表面的一部分上; 沟槽形成在第二基底层的每一侧上，并且形成为比第二基底层更深; 在所述第二基底层的表面上沿着所述沟槽形成的发射极层; 设置在与第一表面相对的第一基底层的第二表面上的第二导电类型的集电极层; 形成在所述沟槽的内壁上的绝缘膜，所述绝缘膜在所述沟槽的底部比在所述沟槽的侧表面上更厚; 形成在所述沟槽内并与所述第二基极层和所述发射极层通过所述绝缘膜隔离的栅电极; 以及设置在彼此相邻的第二基底层之间的空间部分，空间部分比第二基底层更深，并且与发射极层和第二基底层电隔离。

公开(公告)号：US07456487B2

公开(公告)日：2008-11-25

申请号：US10974810

申请日：2004-10-28

申请人： Tsuneo Ogura ,  Masakazu Yamaguchi ,  Tomoki Inoue ,  Hideaki Ninomiya ,  Koichi Sugiyama

发明人： Tsuneo Ogura ,  Masakazu Yamaguchi ,  Tomoki Inoue ,  Hideaki Ninomiya ,  Koichi Sugiyama

IPC分类号： H01L29/739

CPC分类号： H01L29/1095 ,  H01L29/0834 ,  H01L29/7397

摘要： This disclosure concerns a semiconductor device that includes a first base layer; second base layers provided on a part of a first surface of the first base layer; trenches formed on each side of the second base layers; an emitter layer formed on a surface of the second base layers; a collector layer provided below a second surface of the first base layer, an insulating film formed on an inner wall of the trench, the insulating film being thicker on a bottom of the trench than on a side surface of the trench; a gate electrode formed within the trench, and isolated by the insulating film; and a space section provided between the second base layers adjacent to each other, the space section being electrically isolated from the emitter layer and the second base layers, wherein the space section includes a semiconductor layer being deeper than the second base layers.

摘要翻译： 本公开涉及包括第一基底层的半导体器件; 设置在所述第一基底层的第一表面的一部分上的第二基底层; 形成在第二基层的每侧的沟槽; 形成在所述第二基底层的表面上的发射极层; 设置在所述第一基底层的第二表面下方的集电极层，形成在所述沟槽的内壁上的绝缘膜，所述绝缘膜在所述沟槽的底部比在所述沟槽的侧表面上更厚; 形成在沟槽内并由绝缘膜隔离的栅电极; 以及设置在彼此相邻的第二基底层之间的空间部分，所述空间部分与发射极层和第二基底层电隔离，其中所述空间部分包括比所述第二基底层更深的半导体层。

公开(公告)号：US20070278566A1

公开(公告)日：2007-12-06

申请号：US11833401

申请日：2007-08-03

申请人： Tsuneo Ogura ,  Tomoki Inoue ,  Hideaki Ninomiya ,  Koichi Sugiyama

发明人： Tsuneo Ogura ,  Tomoki Inoue ,  Hideaki Ninomiya ,  Koichi Sugiyama

IPC分类号： H01L29/78

CPC分类号： H01L29/1095 ,  H01L29/0619 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/083 ,  H01L29/0834 ,  H01L29/7394 ,  H01L29/7397

摘要： A semiconductor device includes a base layer of a first conductivity type, a barrier layer of a first conductivity type formed on the base layer, a trench formed from the surface of the barrier layer to such a depth as to reach a region in the vicinity of an interface between the barrier layer and the base layer, a gate electrode formed in the trench via a gate insulating film, a contact layer of a second conductivity type selectively formed in a surface portion of the barrier layer, a source layer of the first conductivity type selectively formed in the surface portion of the barrier layer so as to contact the contact layer and a side wall of the gate insulating film in the trench, and a first main electrode formed so as to contact the contact layer and the source layer.

摘要翻译： 半导体器件包括第一导电类型的基底层，形成在基底层上的第一导电类型的阻挡层，从阻挡层的表面形成的沟槽到达达到 阻挡层和基底层之间的界面，通过栅极绝缘膜形成在沟槽中的栅极电极，选择性地形成在阻挡层的表面部分中的第二导电类型的接触层，第一导电性的源极层 形成在所述阻挡层的表面部分中以与所述沟槽中的所述接触层和所述栅极绝缘膜的侧壁接触的第一主电极以及与所述接触层和所述源极层接触的第一主电极。

公开(公告)号：US06747295B2

公开(公告)日：2004-06-08

申请号：US10345268

申请日：2003-01-16

申请人： Tomoki Inoue ,  Koichi Sugiyama ,  Hideaki Ninomiya ,  Tsuneo Ogura

发明人： Tomoki Inoue ,  Koichi Sugiyama ,  Hideaki Ninomiya ,  Tsuneo Ogura

IPC分类号： H01L2978

CPC分类号： H01L29/66348 ,  H01L29/7397

摘要： An IGBT has a p-emitter layer and p-base layer, which are arranged on both sides of an n-base layer. A pair of main trenches are formed to extend through the p-base layer and reach the n-base layer. In a current path region interposed between the main trenches, a pair of n-emitter layers are formed on the surface of the p-base layer. A narrowing trench is formed to extend through the p-base layer and reach the n-base layer. The narrowing trench narrows a hole flow path formed from the n-base layer to the emitter electrode through the p-base layer, thereby increasing the hole current resistance.

摘要翻译： IGBT具有布置在n基层的两侧的p发射极层和p基极层。 一对主沟槽形成为延伸穿过p基层并到达n基层。 在介于主沟槽之间的电流路径区域中，在p基层的表面上形成一对n - 发射极层。 形成窄沟以延伸穿过p基层并到达n基层。 窄沟槽通过p基层使从n基层形成的空穴流路变窄到发射极，从而增加空穴电流电阻。

公开(公告)号：US20050263852A1

公开(公告)日：2005-12-01

申请号：US10974810

申请日：2004-10-28

申请人： Tsuneo Ogura ,  Masakazu Yamaguchi ,  Tomoki Inoue ,  Hideaki Ninomiya ,  Koichi Sugiyama

发明人： Tsuneo Ogura ,  Masakazu Yamaguchi ,  Tomoki Inoue ,  Hideaki Ninomiya ,  Koichi Sugiyama

IPC分类号： H01L29/78 ,  H01L27/082 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/739

CPC分类号： H01L29/1095 ,  H01L29/0834 ,  H01L29/7397

摘要： A semiconductor device comprises a first base layer of a first conductivity type; a plurality of second base layers of a second conductivity type, provided on a part of a first surface of the first base layer; trenches formed on each side of the second base layers, and formed to be deeper than the second base layers; an emitter layer formed along the trench on a surface of the second base layers; a collector layer of the second conductivity type, provided on a second surface of the first base layer opposite to the first surface; an insulating film formed on an inner wall of the trench, the insulating film being thicker on a bottom of the trench than on a side surface of the trench; a gate electrode formed within the trench, and isolated from the second base layers and the emitter layer by the insulating film; and a space section provided between the second base layers adjacent to each other, the space section being deeper than the second base layers and being electrically isolated from the emitter layer and the second base layers.

摘要翻译： 半导体器件包括第一导电类型的第一基极层; 多个第二导电类型的第二基层，设置在所述第一基底层的第一表面的一部分上; 沟槽形成在第二基底层的每一侧上，并且形成为比第二基底层更深; 在所述第二基底层的表面上沿着所述沟槽形成的发射极层; 设置在与第一表面相对的第一基底层的第二表面上的第二导电类型的集电极层; 形成在所述沟槽的内壁上的绝缘膜，所述绝缘膜在所述沟槽的底部比在所述沟槽的侧表面上更厚; 形成在所述沟槽内并与所述第二基极层和所述发射极层通过所述绝缘膜隔离的栅电极; 以及设置在彼此相邻的第二基底层之间的空间部分，空间部分比第二基底层更深，并且与发射极层和第二基底层电隔离。

公开(公告)号：US06891224B2

公开(公告)日：2005-05-10

申请号：US10461345

申请日：2003-06-16

申请人： Tsuneo Ogura ,  Tomoki Inoue ,  Hideaki Ninomiya ,  Koichi Sugiyama

发明人： Tsuneo Ogura ,  Tomoki Inoue ,  Hideaki Ninomiya ,  Koichi Sugiyama

IPC分类号： H01L29/78 ,  H01L21/8228 ,  H01L29/06 ,  H01L29/10 ,  H01L29/739 ,  H01L29/76 ,  H01L29/94 ,  H01L31/0328 ,  H01L31/0336 ,  H01L31/062 ,  H01L31/072 ,  H01L31/109

CPC分类号： H01L29/1095 ,  H01L29/0619 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/083 ,  H01L29/0834 ,  H01L29/7394 ,  H01L29/7397

摘要： A semiconductor device includes: a base layer of a first conductivity type, a barrier layer of a first conductivity type formed on the base layer, a well layer of a second conductivity type formed on the barrier layer; a trench formed from the surface of the well layer to such a depth as to reach a region in the vicinity of a junction surface between the barrier layer and the base layer, a gate electrode formed in the trench via a gate insulating film, a contact layer of the second conductivity type selectively formed in a surface portion of the well layer, a source layer of the first conductivity type selectively formed in the surface portion of the well layer so as to contact a side wall of the gate insulating film in the trench and the contact layer, and a first main electrode formed so as to contact the contact layer and the source layer, wherein assuming that a total sum of impurity densities in the region of the barrier layer between the trenches is Qn, the Qn has a relation of the following equation: Qn≧2×1012 cm−2.

摘要翻译： 半导体器件包括：形成在第一导电类型的基底层，形成在基底层上的第一导电类型的势垒层，形成在阻挡层上的第二导电类型的阱层; 从阱层的表面形成的沟槽到达阻挡层和基底层之间的接合面附近的区域的深度，通过栅极绝缘膜形成在沟槽中的栅电极， 选择性地形成在阱层的表面部分中的第二导电类型的层，选择性地形成在阱层的表面部分中以与沟槽中的栅极绝缘膜的侧壁接触的第一导电类型的源极层 以及形成为与接触层和源极层接触的第一主电极，其中假设沟槽之间的势垒层的区域中的杂质浓度的总和为Qn，则Qn具有关系 具有以下等式：Qn> = 2×10×12