公开(公告)号：US08578227B2

公开(公告)日：2013-11-05

申请号：US12944787

申请日：2010-11-12

Applicant: Young-Jae Son ,  Yong-Jin Yoon ,  Uk-Rae Cho

Inventor： Young-Jae Son ,  Yong-Jin Yoon ,  Uk-Rae Cho

IPC: G01R31/28

CPC classification number: G01R31/31725 ,  G06F11/24

Abstract: A test device for a system-on-chip includes a sequential logic circuit and a test circuit. The sequential logic circuit generates a test input signal by converting a serial input signal into a parallel format in response to a serial clock signal and a serial enable signal and generates a serial output signal by converting a test output signal into a serial format in response to the serial clock signal and the serial enable signal. The test circuit includes at least one delay unit that is separated from a logic circuit performing original functions of the system-on-chip, performs a delay test on the at least one delay unit using the test input signal in response to a system clock signal and a test enable signal, and provides the test output signal to the sequential logic circuit, where the test output signal representing a result of the delay test.

Abstract translation: 用于片上系统的测试装置包括顺序逻辑电路和测试电路。 顺序逻辑电路通过根据串行时钟信号和串行使能信号将串行输入信号转换为并行格式产生测试输入信号，并通过将测试输出信号转换成串行格式来响应于 串行时钟信号和串行使能信号。 测试电路包括至少一个延迟单元，其与执行片上系统的原始功能的逻辑电路分离，响应于系统时钟信号，使用测试输入信号对至少一个延迟单元执行延迟测试 和测试使能信号，并将测试输出信号提供给顺序逻辑电路，其中测试输出信号表示延迟测试的结果。

公开(公告)号：US07154312B2

公开(公告)日：2006-12-26

申请号：US11031129

申请日：2005-01-07

Applicant: Nam-Seog Kim ,  Yong-Jin Yoon ,  Uk-Rae Cho

Inventor： Nam-Seog Kim ,  Yong-Jin Yoon ,  Uk-Rae Cho

IPC: H03L7/00

CPC classification number: H03L7/0812 ,  H03K5/133 ,  H03K5/135

Abstract: An apparatus for generating an internal clock signal for acquisition of accurate synchronization is provided. The apparatus including: an input buffer for buffering the external clock signal to output a first reference clock signal; a delay compensation circuit for delaying the first reference clock signal; a forward delay array; a mirror control circuit comprising a plurality of phase detectors for detecting delayed clock signals synchronized with a second reference clock signal; a backward delay array; and an output buffer to generate an internal clock signal. An internal clock signal in accurate synchronization with the reference clock signal can be generated by minimizing the delay and distortion of the reference clock signal.

Abstract translation: 提供了一种用于产生用于获取精确同步的内部时钟信号的装置。 该装置包括：输入缓冲器，用于缓冲外部时钟信号以输出第一参考时钟信号; 延迟补偿电路，用于延迟第一参考时钟信号; 前向延迟阵列 镜控制电路，包括用于检测与第二参考时钟信号同步的延迟时钟信号的多个相位检测器; 后向延迟阵列 以及产生内部时钟信号的输出缓冲器。 可以通过最小化参考时钟信号的延迟和失真来产生与参考时钟信号精确同步的内部时钟信号。

公开(公告)号：US20050194995A1

公开(公告)日：2005-09-08

申请号：US11071433

申请日：2005-03-03

Applicant: Nam-Seog Kim ,  Yong-Jin Yoon ,  Uk-Rae Cho

Inventor： Nam-Seog Kim ,  Yong-Jin Yoon ,  Uk-Rae Cho

IPC: H03F3/45 ,  G11C7/10

CPC classification number: H03K3/356139

Abstract: Provided is an amplifier circuit having a constant output swing range and a stable delay time, where the amplifier circuit includes a first bias unit, a second bias unit, a comparison unit, and an amplifier unit, and the first bias unit responds to an internal reference signal with a predetermined voltage level and maintains constant the amount of a first current, and the second bias unit receives an external reference signal, responds to a control voltage, and controls the amount of a second current to be the same as the amount of the first current, and the comparison unit compares a voltage level of a first node with a voltage level of a second node, and controls a voltage level of the control voltage according to the comparison result, and the amplifier unit compares a voltage level of an external input signal with a voltage level of the external reference signal, amplifies and outputs a voltage difference between the two compared signals, responds to the control voltage, and controls the amount of a third current to be the same as the amount of the first current although the level of the external reference signal is varied, such that the amplifier circuit and a circuit for receiving data can maintain a constant output swing range and a stable delay time irrespective of variations in the voltage levels of the external input signal or the external reference signal.

Abstract translation: 提供了具有恒定的输出摆幅范围和稳定延迟时间的放大器电路，其中放大器电路包括第一偏置单元，第二偏置单元，比较单元和放大器单元，并且第一偏置单元响应内部 具有预定电压电平的参考信号并且保持第一电流的量的恒定，并且第二偏置单元接收外部参考信号，响应于控制电压，并且将第二电流的量控制为与第 第一电流和比较单元将第一节点的电压电平与第二节点的电压电平进行比较，并且根据比较结果控制控制电压的电压电平，并且放大器单元将电压电平 具有外部参考信号电压电平的外部输入信号，放大并输出两个比较信号之间的电压差，响应控制电压，并控制 尽管外部参考信号的电平变化，但是第三电流的量与第一电流的量相同，使得放大器电路和用于接收数据的电路可以保持恒定的输出摆幅范围和稳定的 延迟时间，而不管外部输入信号或外部参考信号的电压电平的变化。

公开(公告)号：US06617894B2

公开(公告)日：2003-09-09

申请号：US10081359

申请日：2002-02-20

Applicant: Yong-Jin Yoon ,  Uk-Rae Cho ,  Jung-Woo Park ,  Kwang-Jin Lee ,  Nam-Seog Kim

Inventor： Yong-Jin Yoon ,  Uk-Rae Cho ,  Jung-Woo Park ,  Kwang-Jin Lee ,  Nam-Seog Kim

IPC: H03L700

CPC classification number: G06F1/10 ,  H03K5/135

Abstract: A circuit includes a clock buffer to generate an initial reference clock signal responsive to an external clock signal, a DMC to receive the initial reference clock signal, and an array of forward units to receive a signal from the DMC. The circuit also includes an array of back units that produces a back signal. The back signal is input in a clock driver to produce an internal clock signal. A delay element produces a delayed reference signal responsive to the initial reference clock signal. A plurality of MCCs receive an output of one of the forward units and the delayed reference clock signal. When one of the outputs of the forward units is synchronized with the delayed reference clock signal, one of the back units is thereby activated, which initiates generation of the back signal.

公开(公告)号：US07187214B2

公开(公告)日：2007-03-06

申请号：US11071433

申请日：2005-03-03

Applicant: Nam-Seog Kim ,  Yong-Jin Yoon ,  Uk-Rae Cho

Inventor： Nam-Seog Kim ,  Yong-Jin Yoon ,  Uk-Rae Cho

IPC: H03K5/22

CPC classification number: H03K3/356139

Abstract: Provided is an amplifier circuit having a constant output swing range and a stable delay time, where the amplifier circuit includes a first bias unit, a second bias unit, a comparison unit, and an amplifier unit, and the first bias unit responds to an internal reference signal with a predetermined voltage level and maintains constant the amount of a first current, and the second bias unit receives an external reference signal, responds to a control voltage, and controls the amount of a second current to be the same as the amount of the first current, and the comparison unit compares a voltage level of a first node with a voltage level of a second node, and controls a voltage level of the control voltage according to the comparison result, and the amplifier unit compares a voltage level of an external input signal with a voltage level of the external reference signal, amplifies and outputs a voltage difference between the two compared signals, responds to the control voltage, and controls the amount of a third current to be the same as the amount of the first current although the level of the external reference signal is varied, such that the amplifier circuit and a circuit for receiving data can maintain a constant output swing range and a stable delay time irrespective of variations in the voltage levels of the external input signal or the external reference signal.

Abstract translation: 提供了具有恒定的输出摆幅范围和稳定延迟时间的放大器电路，其中放大器电路包括第一偏置单元，第二偏置单元，比较单元和放大器单元，并且第一偏置单元响应内部 具有预定电压电平的参考信号并且保持第一电流的量的恒定，并且第二偏置单元接收外部参考信号，响应于控制电压，并且将第二电流的量控制为与第 第一电流和比较单元将第一节点的电压电平与第二节点的电压电平进行比较，并且根据比较结果控制控制电压的电压电平，并且放大器单元将电压电平 具有外部参考信号电压电平的外部输入信号，放大并输出两个比较信号之间的电压差，响应控制电压，并控制 尽管外部参考信号的电平变化，但是第三电流的量与第一电流的量相同，使得放大器电路和用于接收数据的电路可以保持恒定的输出摆幅范围和稳定的 延迟时间，而不管外部输入信号或外部参考信号的电压电平的变化。

公开(公告)号：US06992514B2

公开(公告)日：2006-01-31

申请号：US10790601

申请日：2004-03-01

Applicant: Nam-Seog Kim ,  Yong-Jin Yoon ,  Uk-Rae Cho

Inventor： Nam-Seog Kim ,  Yong-Jin Yoon ,  Uk-Rae Cho

IPC: H03L7/00

CPC classification number: H03K5/135

Abstract: Disclosed is a synchronous mirror delay circuit for generating an internal clock signal synchronized with an external clock signal, comprising: a clock buffer circuit that generates a reference clock signal in response to the external clock signal; a delay monitor circuit that delays the reference clock signal; a forward delay array for delaying an output clock signal of the delay monitor circuit to generate delay clock signals; a mirror control circuit that receives the delay clock signals and the reference clock signal to detect one delay clock signal synchronized with the reference clock signal among the delay clock signals; a backward delay array that delays the delay clock signal detected by the mirror control circuit to output a synchronous clock signal; a delay circuit that delays an asynchronous clock signal output through the forward delay array; and a clock driving circuit that outputs the delayed asynchronous clock signal as the internal clock signal when the reference clock signal is not synchronized with one of the delay clock signals.

Abstract translation: 公开了一种用于产生与外部时钟信号同步的内部时钟信号的同步镜延迟电路，包括：时钟缓冲电路，其响应于外部时钟信号产生参考时钟信号; 延迟监视电路，延迟参考时钟信号; 用于延迟延迟监视电路的输出时钟信号以产生延迟时钟信号的正向延迟阵列; 接收所述延迟时钟信号和所述参考时钟信号以在所述延迟时钟信号中检测与所述参考时钟信号同步的一个延迟时钟信号的镜像控制电路; 后延迟阵列，其延迟由所述镜控制电路检测到的延迟时钟信号，以输出同步时钟信号; 延迟电路，延迟通过前向延迟阵列输出的异步时钟信号; 以及时钟驱动电路，当所述参考时钟信号与所述延迟时钟信号之一不同步时，输出所述延迟异步时钟信号作为所述内部时钟信号。

公开(公告)号：US20050157827A1

公开(公告)日：2005-07-21

申请号：US11037602

申请日：2005-01-18

Applicant: Yong-Jin Yoon ,  Jong-Cheol Lee ,  Uk-Rae Cho

Inventor： Yong-Jin Yoon ,  Jong-Cheol Lee ,  Uk-Rae Cho

IPC: G11C11/417 ,  G11C7/10 ,  G11C11/40 ,  H04L7/00

CPC classification number: G11C7/1087 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1093

Abstract: A method and circuit for sampling and writing data in a double data rate (DDR) memory device, capable of securing sufficient setup and hold margins regardless of the operation frequency. Transferring first and second sampled input data to a first path using a first path control signal. Transferring third and fourth sampled input data to a second path using a second path control signal. The first and second path control signals are one half-cycle out of phase. First to fourth data are successively sampled in synchronization with a rising or falling edge of a first external clock signal; The sampled first data is linked onto a first path and the sampled second data is linked onto a second path in response to the first path control signal (generated in synchronization with a falling edge of the external clock signal); the first data on the first path and the second data on the second path are written to the memory cells in response to a write clock signal.

Abstract translation: 一种用于在双倍数据速率（DDR）存储器件中采样和写入数据的方法和电路，能够确保足够的设置和保持余量而不考虑操作频率。 使用第一路径控制信号将第一和第二采样输入数据传送到第一路径。 使用第二路径控制信号将第三和第四采样输入数据传送到第二路径。 第一和第二路径控制信号是相位相差一个半周期。 与第一外部时钟信号的上升沿或下降沿同步地连续采样第一至第四数据; 响应于第一路径控制信号（与外部时钟信号的下降沿同步产生），采样的第一数据被链接到第一路径上，并且采样的第二数据被链接到第二路径上。 响应于写入时钟信号将第一路径上的第一数据和第二路径上的第二数据写入存储器单元。

公开(公告)号：US06661272B2

公开(公告)日：2003-12-09

申请号：US10041060

申请日：2002-01-07

Applicant: Nam-Seog Kim ,  Yong-Jin Yoon

Inventor： Nam-Seog Kim ,  Yong-Jin Yoon

IPC: H03K300

CPC classification number: G11C7/222 ,  G11C7/22

Abstract: An internal clock generating circuit of a semiconductor device includes: a delay chain having a plurality of delay units for generating multi-phase clocks by adjusting an input clock; a thermometer for outputting a thermometer code value in response to an input selection data; a multiplexer for selectively outputting one of a plurality of clocks input from the delay chain in response to the thermometer code value of the thermometer; and a pulse regenerator for outputting an adjusted internal clock by restoring a pulse form of the clock output from the multiplexer into its original state and controlling the delay thereof as much as desired.