公开(公告)号：US20230071946A1

公开(公告)日：2023-03-09

申请号：US17707964

申请日：2022-03-30

Applicant: Industrial Technology Research Institute

Inventor： Chieh-Wei Feng ,  Tai-Jui Wang ,  Jui-Wen Yang ,  Tzu-Yang Ting

IPC: H01L23/498 ,  G01R1/073 ,  H01L23/66

Abstract: The present disclosure provides a package structure, an antenna module, and a probe card. The package structure includes a connection member and a first redistribution structure disposed on the connection member. The connection member includes a conductive connector and an insulation layer surrounding the conductive connector. The first redistribution structure includes a first dielectric layer, and a first wiring pattern, and a first device. The first dielectric layer is disposed on the connection member. The first wiring pattern is disposed in the first dielectric layer. The first device is disposed above the first dielectric layer and is electrically connected to the conductive connector.

公开(公告)号：US20220173055A1

公开(公告)日：2022-06-02

申请号：US17158014

申请日：2021-01-26

Applicant: Industrial Technology Research Institute

Inventor： Tzu-Yang Ting ,  Chieh-Wei Feng ,  Tai-Jui Wang

IPC: H01L23/64 ,  H01L23/498 ,  H01L49/02 ,  H01L23/552 ,  H01G4/30 ,  H01G4/012 ,  H01G4/40 ,  H01F27/40 ,  H03H7/01

Abstract: Provided are a capacitor and a filter and a redistribution layer structure including the same. The capacitor includes a first electrode, a second electrode, a third electrode, a dielectric layer, and a conductive through via. The second electrode is disposed above the first electrode. The third electrode is disposed between the first electrode and the second electrode. The dielectric layer is disposed between the first electrode and the third electrode and between the second electrode and the third electrode. The conductive through via penetrates the dielectric layer and the third electrode to be connected to the first electrode and the second electrode, and is electrically separated from the third electrode. The first electrode and the second electrode are signal electrodes, and the third electrode is a ground electrode.

公开(公告)号：US11088135B2

公开(公告)日：2021-08-10

申请号：US16406032

申请日：2019-05-08

Applicant: Industrial Technology Research Institute

Inventor： Yu-Hua Chung ,  Tai-Jui Wang ,  Chieh-Wei Feng

IPC: H01L27/02 ,  H01L23/60 ,  H01L23/522

Abstract: An electrostatic discharge (ESD) protection apparatus and an integrated passive device (IPD) with capacitor(s) are provided. The ESD protection apparatus includes a transistor, an impedance, and a capacitor disposed in a redistribution layer (RDL) structure of a package. The first terminal and the second terminal of the transistor are respectively coupled to a first power rail and a second power rail of the RDL structure. A first terminal of the impedance is coupled to the first power rail. A second terminal of the impedance is coupled to a control terminal of the transistor. A first terminal of the capacitor is coupled to the second terminal of the impedance. A second terminal of the capacitor is coupled to the second power rail.

公开(公告)号：US10941498B2

公开(公告)日：2021-03-09

申请号：US16447358

申请日：2019-06-20

Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

Inventor： Chien-Hsun Chu ,  Chien-Chou Tseng ,  Ming-Huan Yang ,  Tai-Jui Wang ,  Yu-Hua Chung ,  Chieh-Wei Feng

IPC: H01L29/40 ,  C25D5/02 ,  C25D7/12 ,  H01L23/528 ,  H01L21/288

Abstract: A panel to be plated is provided. The panel includes a substrate and an electric field compensation structure. The substrate includes a plurality of units to be plated each including a first pattern to be plated. The electric field compensation structure is disposed on the substrate. The electric field compensation structure includes a second pattern to be plated surrounding at least one of the units to be plated. A ratio of an area of the first pattern to be plated of the units to be plated to an area of the second pattern to be plated of the electric field compensation structure is in a range from 1:0.07 to 1:0.3.

公开(公告)号：US20250126722A1

公开(公告)日：2025-04-17

申请号：US18916714

申请日：2024-10-16

Applicant: Industrial Technology Research Institute

Inventor： Chieh-Wei Feng ,  Cheng-Yueh Chang ,  Tai-Jui Wang

IPC: H05K3/40 ,  H05K1/11 ,  H05K1/18

Abstract: A circuit compensation method applied to pattern displacement includes: disposing at least one chip on a carrier; measuring a shift of the chip, performing circuit position compensation on a predetermined pattern of a redistribution layer, and calculating a resistance difference of the pattern before and after the circuit position compensation; estimating a circuit proportion and a range of resistance variation in the pattern needed for resistance compensation after the circuit position compensation according to the resistance difference; determining a compensation position and a scheme of circuit proportion and adjusting a circuit width, area, length, pattern, or combination thereof of a circuit within the circuit proportion according to the resistance difference; outputting a picture file of the pattern after the circuit position and resistance compensation; and forming the redistribution layer according to the picture file and electrically connecting the redistribution layer to the chip. A circuit structure is also provided.

公开(公告)号：US20240130657A1

公开(公告)日：2024-04-25

申请号：US18454074

申请日：2023-08-23

Applicant: Industrial Technology Research Institute

Inventor： Hsien-Wei Chiu ,  Tai-Jui Wang ,  Chieh-Wei Feng ,  Jui-Wen Yang

IPC: A61B5/27 ,  A61B5/00

CPC classification number: A61B5/27 ,  A61B5/6804

Abstract: A physiological sensing device for sensing physiological signal of an organism is provided. The physiological sensing device includes a sensing chip, a coupling sensing electrode and a coupling dielectric stacked layer. The coupling sensing electrode is electrically connected to the sensing chip. The coupling dielectric stacked layer covers the coupling sensing electrode. The coupling dielectric stacked layer is located between the coupling sensing electrode and the organism. The coupling dielectric stacked layer includes a first dielectric layer and a second dielectric layer. The dielectric constant of the second dielectric layer is greater than that of the first dielectric layer. The second dielectric layer is located between the first dielectric layer and the organism.

公开(公告)号：US11839120B2

公开(公告)日：2023-12-05

申请号：US17037737

申请日：2020-09-30

Applicant: Industrial Technology Research Institute

Inventor： Wei-Chung Chen ,  Wen-Yu Kuo ,  Chieh-Wei Feng ,  Tai-Jui Wang

IPC: H10K59/131 ,  H10K59/121 ,  H10K59/122

CPC classification number: H10K59/131 ,  H10K59/121 ,  H10K59/122

Abstract: An electronic device including a pixel array structure, a redistribution structure, and a plurality of conductive via structures is provided. The pixel array structure includes a plurality of signal lines. The redistribution structure overlaps the pixel array structure and includes a plurality of conductive lines. The conductive via structures electrically connect the signal lines of the pixel array structure and the conductive lines of the redistribution structure. At least one of the conductive via structures shares at least one conductive layer with the pixel array structure.

公开(公告)号：US11387230B2

公开(公告)日：2022-07-12

申请号：US16183735

申请日：2018-11-08

Applicant: Industrial Technology Research Institute

Inventor： Cheng-Hung Yu ,  Tai-Jui Wang ,  Chieh-Wei Feng ,  Yu-Hua Chung

IPC: H01L27/02 ,  H02H9/04 ,  H01L23/538 ,  H01L27/12

Abstract: A system in package structure and an electrostatic discharge protection structure thereof are provided. The electrostatic discharge protection structure includes a redistribution layer and a first transistor array. The redistribution layer has a first electrode and a second electrode. The first transistor array is coupled to a pin end of at least one integrated circuit, the first electrode and the second electrode. The first transistor array has a plurality of transistors. A plurality of first transistors of the transistors are coupled in parallel, and a plurality of second transistors of the transistors are coupled in parallel. The first transistors and the second transistors are configured to be turned on for dissipating an electrostatic discharge current.

公开(公告)号：US20190341373A1

公开(公告)日：2019-11-07

申请号：US16027374

申请日：2018-07-05

Applicant: Industrial Technology Research Institute

Inventor： Cheng-Hung Yu ,  Tai-Jui Wang ,  Chieh-Wei Feng ,  Wei-Yuan Cheng

IPC: H01L25/16 ,  H01L23/31 ,  H01L23/538 ,  H01L23/60 ,  H01L23/00 ,  H01L25/00 ,  H01L21/48 ,  H01L21/56

Abstract: A chip package structure including a redistribution structure layer, at least one chip, and an encapsulant is provided. The redistribution structure layer includes at least one redistribution circuit, at least one transistor electrically connected to the redistribution circuit, and a plurality of conductive vias electrically connected to the redistribution circuit and the transistor. The chip is disposed on the redistribution structure layer and electrically connected to the redistribution structure layer. The encapsulant is disposed on the redistribution structure layer and at least encapsulates the chip. A manufacturing method of a chip package structure is also provided.

公开(公告)号：US20170186367A1

公开(公告)日：2017-06-29

申请号：US14983548

申请日：2015-12-30

Applicant: Industrial Technology Research Institute

Inventor： Yu-Hua Jhong ,  Tsu-Chiang Chang ,  Tai-Jui Wang

IPC: G09G3/3225 ,  G09G3/36

CPC classification number: G09G3/3225 ,  G09G3/3648 ,  G09G2300/0426 ,  H01L27/124

Abstract: A pixel array structure including a bottom carrier plate, a wire layer, a planarization layer, a pixel unit layer and a conductor structure is provided. The wire layer is disposed on the bottom carrier plate. The planarization layer covers the wire layer and has a flat surface at a side away from the wire layer. The pixel unit layer is disposed on the flat surface of the planarization layer. The pixel unit layer includes a pixel unit including a driving circuit structure and a pixel electrode electrically connected to the driving circuit structure. The conductor structure passes through the planarization layer and is connected between the driving circuit structure and the wire layer. A display panel having the pixel array structure and a method of fabricating the pixel array structure are also provided.