公开(公告)号：US20240098389A1

公开(公告)日：2024-03-21

申请号：US18524008

申请日：2023-11-30

Applicant: Infineon Technologies AG

Inventor： Wolfgang Budde ,  Jens de Bock ,  Daniel Domes ,  Andreas Lenniger ,  Bjoern Rentemeister ,  Stefan Hubert Schmies ,  Andreas Vetter

IPC: H04Q9/00

CPC classification number: H04Q9/00 ,  H04Q2209/10 ,  H04Q2209/84

Abstract: An electronic device includes an interface configured to receive telemetry information for one or more power semiconductor devices and a data acquisition and processing unit. The data acquisition and processing unit may be configured to increase a gate voltage above a maximum permitted level for each of the one or more power semiconductor devices having a current slew rate that exceeds a predetermined level as determined by the telemetry information. The data acquisition and processing unit may be configured to increase a gate voltage above a maximum permitted level for each of the one or more power semiconductor devices having a temperature that exceeds a predetermined level as determined by the telemetry information. An electronic system that includes the electronic device is also described.

公开(公告)号：US20220173078A1

公开(公告)日：2022-06-02

申请号：US17676410

申请日：2022-02-21

Applicant: Infineon Technologies AG

Inventor： Daniel Domes

IPC: H01L25/07 ,  H01L23/367 ,  H01L23/50 ,  H01L25/18

Abstract: A semiconductor arrangement includes at least two switching devices of a first type electrically coupled in parallel between first and second terminals, and at least two switching devices of a second type electrically coupled in parallel between the second terminal and a third terminal. One first diode is electrically coupled in parallel to each switching device of the first type. One second diode is electrically coupled in parallel to each switching device of the second type. The switching devices are arranged in a power semiconductor module having first and second longitudinal sides and first and second narrow sides. The first type switching devices and first diodes are arranged alternatingly in one row along the first longitudinal side. The second type switching devices and second diodes are arranged alternatingly in another row along the second longitudinal side. An axis of symmetry that extends perpendicular to the first and second narrow sides.

公开(公告)号：US11843368B2

公开(公告)日：2023-12-12

申请号：US18060639

申请日：2022-12-01

Applicant: Infineon Technologies AG

Inventor： Zheming Li ,  Mark-Matthias Bakran ,  Daniel Domes ,  Robert Maier ,  Franz-Josef Niedernostheide

IPC: H03K17/04 ,  H03K17/042 ,  H03K5/24

CPC classification number: H03K17/04206 ,  H03K5/24 ,  H03K17/042 ,  H03K17/0406

Abstract: A method is provided for driving a half bridge circuit that includes a first transistor and a second transistor. The method includes generating an off-current during a plurality of turn-off switching events to control a gate voltage of the second transistor; measuring a transistor parameter of the second transistor during a first turn-off switching event during which the second transistor is transitioned to an off state, wherein the transistor parameter is indicative of an oscillation at the first transistor during a corresponding turn-on switching event during which the first transistor is transitioned to an on state; and activating a portion of the off-current for the second turn-off switching event, including regulating an interval length of the second portion for the second turn-off switching event based on the measured transistor parameter measured during the first turn-off switching event.

公开(公告)号：US20220060184A1

公开(公告)日：2022-02-24

申请号：US17402515

申请日：2021-08-14

Applicant: Infineon Technologies AG

Inventor： Daniel Domes

IPC: H03K17/0812

Abstract: Switch modules, driver circuits for switch modules and corresponding methods are provided. In an implementation, a switch module includes a transistor switch including a control terminal, a first load terminal and a second load terminal, and a short circuit detection circuit configured to detect a short circuit state between the first load terminal and the second load terminal and to electrically couple the control terminal and the first load terminal in response to detecting the short circuit state. The short circuit detection circuit is supplied by a voltage between the control terminal and the first load terminal.

公开(公告)号：US11031929B1

公开(公告)日：2021-06-08

申请号：US16943318

申请日：2020-07-30

Applicant: Infineon Technologies AG

Inventor： Robert Maier ,  Mark-Matthias Bakran ,  Daniel Domes ,  Zheming Li ,  Franz-Josef Niedernostheide

IPC: H03K17/042 ,  H03K17/687 ,  H03K17/95

Abstract: A method of driving a transistor includes generating an off-current during a plurality of turn-off switching events to control a gate voltage at a gate terminal of the transistor, wherein generating the off-current includes sinking a first portion of the off-current from the gate terminal to discharge a first portion of the gate voltage, and sinking, during a boost interval, a second portion of the off-current from the gate terminal to discharge a second portion of the gate voltage; measuring a transistor parameter indicative of an oscillation of a drain-source voltage of the transistor for a first turn-off switching event during which the transistor is transitioned off; activating the first portion of the off-current for a second turn-off switching event; and activating the second portion of the off-current for the second turn-off switching event, including regulating a length of the boost interval based on the measured transistor parameter.

公开(公告)号：US10475909B2

公开(公告)日：2019-11-12

申请号：US15608137

申请日：2017-05-30

Applicant: Infineon Technologies AG

Inventor： Thomas Basler ,  Roman Baburske ,  Daniel Domes ,  Johannes Georg Laven ,  Roland Rupp

IPC: H01L21/02 ,  H01L29/739 ,  H03K17/04 ,  H03K17/567

Abstract: An electric assembly includes a bipolar switching device and a transistor circuit. The transistor circuit is electrically connected in parallel with the bipolar switching device and includes a normally-on wide bandgap transistor.

公开(公告)号：US10032755B2

公开(公告)日：2018-07-24

申请号：US15345751

申请日：2016-11-08

Applicant: Infineon Technologies AG

Inventor： Daniel Domes ,  Reinhold Bayerer ,  Waleri Brekel

IPC: H01L25/11 ,  H01L23/367 ,  H01L23/495 ,  H01L23/552 ,  H01L23/64 ,  H02M7/00 ,  H05K7/20 ,  H05K7/14

Abstract: A multiplicity of power semiconductor switching elements of the same type parallel have a load current terminal for a load current input and a load current terminal for a load current output. At least one outer load current terminal and at least one inner load current terminal per load current direction include a load current input and a load current output. At least one contacting device for common electrical contacting all of the load current terminals of the same load current direction includes a load current input and a load current output. The contacting device includes a plurality of terminal tongues which are respectively fastened on an associated load current terminal. The geometry and/or profile of the terminal tongue of an outer load current terminal differs from the geometry and/or profile of the terminal tongue of an inner load current terminal of the same contacting device.

公开(公告)号：US12212309B2

公开(公告)日：2025-01-28

申请号：US17402515

申请日：2021-08-14

Applicant: Infineon Technologies AG

Inventor： Daniel Domes

IPC: H03K17/0812

Abstract: Switch modules, driver circuits for switch modules and corresponding methods are provided. In an implementation, a switch module includes a transistor switch including a control terminal, a first load terminal and a second load terminal, and a short circuit detection circuit configured to detect a short circuit state between the first load terminal and the second load terminal and to electrically couple the control terminal and the first load terminal in response to detecting the short circuit state. The short circuit detection circuit is supplied by a voltage between the control terminal and the first load terminal.

公开(公告)号：US12088283B2

公开(公告)日：2024-09-10

申请号：US18350790

申请日：2023-07-12

Applicant: Infineon Technologies AG

Inventor： Zheming Li ,  Mark-Matthias Bakran ,  Daniel Domes ,  Robert Maier ,  Franz-Josef Niedernostheide

IPC: H03K17/042 ,  H03K17/04

CPC classification number: H03K17/0406 ,  H03K17/042 ,  H03K17/04206 ,  H03K2217/0027

Abstract: A gate driver system includes a gate driver circuit coupled to a gate terminal of a transistor and configured to control a gate voltage to generate an on-current during a plurality of turn-on switching events to turn on the transistor. The gate driver circuit includes a first driver configured to source a first portion of the on-current to the gate terminal to charge a first portion of the gate voltage, and a second driver configured to, during a boost interval, source a second portion of the on-current to the gate terminal to charge a second portion of the gate voltage. A control circuit measures a transistor parameter representative of a reverse recovery current of the transistor for a turn-on switching event during which the transistor is transitioned to an on state and controls the first driver and controls the second driver based on the measured transistor parameter.

公开(公告)号：US11889246B1

公开(公告)日：2024-01-30

申请号：US17857615

申请日：2022-07-05

Applicant: Infineon Technologies AG

Inventor： Wolfgang Budde ,  Jens de Bock ,  Daniel Domes ,  Andreas Lenniger ,  Bjoern Rentemeister ,  Stefan Hubert Schmies ,  Andreas Vetter

IPC: H04Q9/00

CPC classification number: H04Q9/00 ,  H04Q2209/10 ,  H04Q2209/84

Abstract: An electronic device includes: an interface configured to receive telemetry information for one or more power semiconductor devices; and a data acquisition and processing unit. The data acquisition and processing unit may be configured to periodically update an estimate of a remaining lifetime of the one or more power semiconductor devices, based on the telemetry information collected during use of the one or more power semiconductor devices and received at the interface. The data acquisition and processing unit may be configured to adjust one or more operating parameters for each of the one or more power semiconductor devices that has reached a predetermined level of degradation as determined by the telemetry information. An electronic system that includes the electronic device is also described.